android-x86-mesa.git/src/mesa/drivers/dri/i965/Makefile, branch r300Androïd/x86 port of Mesa drivers
https://git.hiegel.fr/cgit/android-x86-mesa.git/atom?h=r3002011-01-20T00:29:11Zi965/fs: Add an instruction scheduler.2011-01-20T00:29:11ZEric Anholteric@anholt.net2011-01-19T01:16:49Zurn:sha1:63879d90ace519749fed228ca0e21b5b56c7e1c0
Improves performance of my GLSL demo by 5.1% (+/- 1.4%, n=7). It also
reschedules the giant multiply tree at the end of
glsl-fs-convolution-1 so that we end up not spilling registers,
producing the expected level of performance.
i965: Nuke brw_wm_glsl.c.2010-12-06T08:14:23ZEric Anholteric@anholt.net2010-11-11T17:09:38Zurn:sha1:5ba517baa22b05d594b8839ac06fe45b81c1d09f
It was only used for gen6 fragment programs (not GLSL shaders) at this
point, and it was clearly unsuited to the task -- missing opcodes,
corrupted texturing, and assertion failures hit various applications
of all sorts. It was easier to patch up the non-glsl for remaining
gen6 changes than to make brw_wm_glsl.c complete.
Bug #30530
i965: Split register allocation out of the ever-growing brw_fs.cpp.2010-10-21T22:20:01ZEric Anholteric@anholt.net2010-10-20T17:26:29Zurn:sha1:5ac6c4ecfe77bf7e02ae61981b2c8b1fe73027cdi965: Normalize cubemap coordinates like is done in the Mesa IR path.2010-10-07T23:41:13ZEric Anholteric@anholt.net2010-10-06T05:30:42Zurn:sha1:bbb840049e7a92af6e0e8c2c5c21c63caec9e826
Fixes glsl-fs-texturecube-2-*
i965: Add new pass to split vectors into scalar variables2010-08-26T21:55:44ZEric Anholteric@anholt.net2010-08-26T19:02:26Zurn:sha1:c1dfdcb93a8991788032d4906c5bf1a5b48cdc48
Combined with the previous pass, this lets other optimization passes
do their work thanks to ir_tree_grafting. Still have regression in
instruction count with INTEL_NEW_FS, but register count is even
better.
i965: Add a pass for the FS to reduce vector expressions down to scalar.2010-08-26T21:55:43ZEric Anholteric@anholt.net2010-08-13T09:20:40Zurn:sha1:3a8ad33dde2f059b82ebf09f5cffa66c86f2e734
This is a step towards implementing a GLSL IR backend for the 965
fragment shader. Because it has downsides with the current codegen,
it is hidden under the environment variable INTEL_NEW_FS.
This results in an increase in instruction count at the moment (1444
-> 1752 for glsl-fs-raytrace, 345 -> 359 on my demo), because dot
products are turned into a series of multiplies and adds instead of a
custom expansion of MULs and MACs, and by not splitting the variable
types up we don't get tree grafting and thus there are extra moves of
temporary storage. However, register count drops for the non-GLSL
path (64 -> 56 on my demo shader) because the register allocator sees
all the sub-operations.
i965: Start building 965 FS backend.2010-08-26T21:55:43ZEric Anholteric@anholt.net2010-08-11T03:39:06Zurn:sha1:a1bebf73dfdaf2cd23286aa74271b87166589901intel: Remove unused intel/server files2010-07-27T19:22:07ZKristian Høgsbergkrh@bitplanet.net2010-07-27T19:21:19Zurn:sha1:7d349f588af88f9c5cfe37a331bcef6292a9111ei965: Set the CC VP state immediately on state change.2010-06-11T07:15:56ZEric Anholteric@anholt.net2010-06-10T05:24:14Zurn:sha1:f5bb775fd1f333d8e579d07a5cac1ded2bd54a2f
The cache lookup of these two little floats was .12% of total CPU time
on firefox-talos-gfx because we did it any time commonly-changed state
changed. On the other hand, updating the CC VP bo immediately whenver
CC VP state changes is a .07% overhead due to putting a driver hoook
in glEnable().
intel: Only register ES2 extensions for ES2 contexts2010-04-28T18:36:45ZKristian Høgsbergkrh@bitplanet.net2010-04-27T18:57:51Zurn:sha1:a5107b0a5cb1ac9f112aa498f57c13580bd56cb3