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authorZhenyu Wang <zhenyuw@linux.intel.com>2010-09-29 13:59:03 +0800
committerZhenyu Wang <zhenyuw@linux.intel.com>2010-09-29 14:02:37 +0800
commit0a1910c26760762eb8d67f68dfd87494ab479e38 (patch)
tree856b04c9a7db710693e53dbf27ec3ee3d4fd9963
parent28b57c56e21943055f8d3c08822c4f632468b0b1 (diff)
i965: Always set tiling for depth buffer on sandybridge
Sandybridge only support tiling depth buffer, always set tiling bit. Fix 'fbo_firecube' demo.
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 6eeaba7772..7a334126f2 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -289,7 +289,7 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(((region->pitch * region->cpp) - 1) |
(format << 18) |
(BRW_TILEWALK_YMAJOR << 26) |
- ((region->tiling != I915_TILING_NONE) << 27) |
+ (1 << 27) |
(BRW_SURFACE_2D << 29));
OUT_RELOC(region->buffer,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,