diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2008-06-18 15:33:33 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2008-06-18 15:33:33 +0800 |
| commit | 3e8aadee8beffaabd4e0c60c289b98124e288dcd (patch) | |
| tree | 9279a053f96abc9b91d0becd5276228a3c0df950 | |
| parent | 30640695400b9b27656893753ae6b62f2082ce9b (diff) | |
i965: add support for Intel 4 series chipsets
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_chipset.h | 12 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.c | 7 |
2 files changed, 17 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 3c8fd2384e..4a5166263a 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -53,7 +53,11 @@ #define PCI_CHIP_I965_GM 0x2A02 #define PCI_CHIP_I965_GME 0x2A12 -#define PCI_CHIP_IGD_GM 0x2A42 +#define PCI_CHIP_IGD_GM 0x2A42 + +#define PCI_CHIP_IGD_E_G 0x2E02 +#define PCI_CHIP_Q45_G 0x2E12 +#define PCI_CHIP_G45_G 0x2E22 #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ @@ -63,7 +67,11 @@ devid == PCI_CHIP_I965_GME || \ devid == PCI_CHIP_IGD_GM) -#define IS_IGD(devid) (devid == PCI_CHIP_IGD_GM) +#define IS_IGD_GM(devid) (devid == PCI_CHIP_IGD_GM) +#define IS_G4X(devid) (devid == PCI_CHIP_IGD_E_G || \ + devid == PCI_CHIP_Q45_G || \ + devid == PCI_CHIP_G45_G) +#define IS_IGD(devid) (IS_IGD_GM(devid) || IS_G4X(devid)) #define IS_915(devid) (devid == PCI_CHIP_I915_G || \ devid == PCI_CHIP_E7221_G || \ diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 47e7d1afc2..80e2111b83 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -167,8 +167,15 @@ intelGetString(GLcontext * ctx, GLenum name) chipset = "Intel(R) 965GME/GLE"; break; case PCI_CHIP_IGD_GM: + case PCI_CHIP_IGD_E_G: chipset = "Intel(R) Integrated Graphics Device"; break; + case PCI_CHIP_G45_G: + chipset = "Intel(R) G45/G43"; + break; + case PCI_CHIP_Q45_G: + chipset = "Intel(R) Q45/Q43"; + break; default: chipset = "Unknown Intel Chipset"; break; |