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authorEric Anholt <eric@anholt.net>2010-01-26 17:47:03 -0800
committerEric Anholt <eric@anholt.net>2010-01-26 18:02:21 -0800
commit41f4d82ba8e2497d9fe27f55cb1b8707862fed46 (patch)
treece374358caae3ae9f9e61afd4e64e2a675b29cc2
parenta389d6bd566ba241a285c3a33039d5e964bc8f30 (diff)
intel: Clean up stale comments about cliprects.
-rw-r--r--src/mesa/drivers/dri/i965/brw_sf_state.c6
-rw-r--r--src/mesa/drivers/dri/intel/intel_batchbuffer.c38
-rw-r--r--src/mesa/drivers/dri/intel/intel_pixel_bitmap.c2
3 files changed, 4 insertions, 42 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 8ebbd09e43..847c886279 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -69,9 +69,9 @@ static void upload_sf_vp(struct brw_context *brw)
* for DrawBuffer->_[XY]{min,max}
*/
- /* The scissor only needs to handle the intersection of drawable and
- * scissor rect. Clipping to the boundaries of static shared buffers
- * for front/back/depth is covered by looping over cliprects in brw_draw.c.
+ /* The scissor only needs to handle the intersection of drawable
+ * and scissor rect, since there are no longer cliprects for shared
+ * buffers with DRI2.
*
* Note that the hardware's coordinates are inclusive, while Mesa's min is
* inclusive but max is exclusive.
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index f18fb91a88..ae0f8a16f9 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -32,44 +32,6 @@
#include "intel_bufmgr.h"
#include "intel_buffers.h"
-/* Relocations in kernel space:
- * - pass dma buffer seperately
- * - memory manager knows how to patch
- * - pass list of dependent buffers
- * - pass relocation list
- *
- * Either:
- * - get back an offset for buffer to fire
- * - memory manager knows how to fire buffer
- *
- * Really want the buffer to be AGP and pinned.
- *
- */
-
-/* Cliprect fence: The highest fence protecting a dma buffer
- * containing explicit cliprect information. Like the old drawable
- * lock but irq-driven. X server must wait for this fence to expire
- * before changing cliprects [and then doing sw rendering?]. For
- * other dma buffers, the scheduler will grab current cliprect info
- * and mix into buffer. X server must hold the lock while changing
- * cliprects??? Make per-drawable. Need cliprects in shared memory
- * -- beats storing them with every cmd buffer in the queue.
- *
- * ==> X server must wait for this fence to expire before touching the
- * framebuffer with new cliprects.
- *
- * ==> Cliprect-dependent buffers associated with a
- * cliprect-timestamp. All of the buffers associated with a timestamp
- * must go to hardware before any buffer with a newer timestamp.
- *
- * ==> Dma should be queued per-drawable for correct X/GL
- * synchronization. Or can fences be used for this?
- *
- * Applies to: Blit operations, metaops, X server operations -- X
- * server automatically waits on its own dma to complete before
- * modifying cliprects ???
- */
-
void
intel_batchbuffer_reset(struct intel_batchbuffer *batch)
{
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
index aaf3a8b889..1e517650b7 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
@@ -103,7 +103,7 @@ static void set_bit( GLubyte *dest, GLuint bit )
}
/* Extract a rectangle's worth of data from the bitmap. Called
- * per-cliprect.
+ * per chunk of HW-sized bitmap.
*/
static GLuint get_bitmap_rect(GLsizei width, GLsizei height,
const struct gl_pixelstore_attrib *unpack,