r600: rework emit code

make sure we allocate enough space for relocs

4 files changed, 44 insertions, 37 deletions

diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
index dc2fb0144a..83687bb720 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
@@ -129,10 +129,10 @@ int r600_cs_write_reloc(struct radeon_cs *cs,
             }
             relocs[i].indices = indices;
             relocs[i].reloc_indices = reloc_indices;
-            relocs[i].indices[relocs[i].cindices - 1] = cs->cdw - 1;
-            relocs[i].reloc_indices[relocs[i].cindices - 1] = cs->section_cdw;
-            cs->section_ndw += 2;
+            relocs[i].indices[relocs[i].cindices - 1] = cs->cdw;
+            relocs[i].reloc_indices[relocs[i].cindices - 1] = cs->cdw;
             cs->section_cdw += 2;
+	    cs->cdw += 2;
 
             return 0;
         }
@@ -156,10 +156,10 @@ int r600_cs_write_reloc(struct radeon_cs *cs,
         return -ENOMEM;
     }
 
-    relocs[cs->crelocs].indices[0] = cs->cdw - 1;
-    relocs[cs->crelocs].reloc_indices[0] = cs->section_cdw;
-    cs->section_ndw += 2;
+    relocs[cs->crelocs].indices[0] = cs->cdw;
+    relocs[cs->crelocs].reloc_indices[0] = cs->cdw;
     cs->section_cdw += 2;
+    cs->cdw += 2;
     relocs[cs->crelocs].cindices = 1;
     cs->relocs_total_size += radeon_bo_legacy_relocs_size(bo);
     cs->crelocs++;
@@ -183,7 +183,14 @@ static int r600_cs_begin(struct radeon_cs *cs,
         return -EPIPE;
     }
 
-    if (cs->cdw + ndw + 32 > cs->ndw) { /* Left 32 DWORD (8 offset+pitch) spare room for reloc indices */
+    cs->section = 1;
+    cs->section_ndw = ndw;
+    cs->section_cdw = 0;
+    cs->section_file = file;
+    cs->section_func = func;
+    cs->section_line = line;
+
+    if (cs->cdw + ndw > cs->ndw) {
         uint32_t tmp, *ptr;
 	int num = (ndw > 0x3FF) ? ndw : 0x3FF;
 
@@ -196,13 +203,6 @@ static int r600_cs_begin(struct radeon_cs *cs,
         cs->ndw = tmp;
     }
 
-    cs->section = 1;
-    cs->section_ndw = 0; 
-    cs->section_cdw = cs->cdw + ndw; /* start of reloc indices. */
-    cs->section_file = file;
-    cs->section_func = func;
-    cs->section_line = line;
-
     return 0;
 }
 
@@ -219,8 +219,7 @@ static int r600_cs_end(struct radeon_cs *cs,
     }
     cs->section = 0;
 
-    if ( (cs->section_ndw + cs->cdw) != cs->section_cdw ) 
-    {
+    if ( cs->section_ndw != cs->section_cdw ) {
         fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
                 cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw);
         fprintf(stderr, "cs->section_ndw = %d, cs->cdw = %d, cs->section_cdw = %d \n",
@@ -230,7 +229,6 @@ static int r600_cs_end(struct radeon_cs *cs,
         return -EPIPE;
     }
 
-    cs->cdw = cs->section_cdw;
     return 0;
 }
 
diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h
index 5df0cf1ab6..06eddf2eee 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h
@@ -143,6 +143,9 @@ extern int r600_cs_write_reloc(struct radeon_cs *cs,
 static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword)
 {
     cs->packets[cs->cdw++] = dword;
+    if (cs->section) {
+	    cs->section_cdw++;
+    }
 }
 
 struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx);
@@ -175,7 +178,6 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont
             fprintf(stderr, "(%s:%s:%d) offset : %d\n",		\
             __FILE__, __FUNCTION__, __LINE__, offset);		\
         }							\
-        r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset);	\
         r600_cs_write_reloc(b_l_rmesa->cmdbuf.cs, 		\
                               bo, rd, wd, flags);		\
 	} while(0)
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index f461d08a70..c3c0923ebb 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -276,11 +276,16 @@ GLboolean r700SendTextureState(context_t *context)
 					 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
 					 0, TC_ACTION_ENA_bit);
 
-			    BEGIN_BATCH_NO_AUTOSTATE(9);
+			    BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
 			    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 			    R600_OUT_BATCH(i * 7);
 			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
 			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
+			    R600_OUT_BATCH(0); /* r700->textures[i]->SQ_TEX_RESOURCE2 */
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
 			    R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
 						 bo,
 						 0,
@@ -289,9 +294,6 @@ GLboolean r700SendTextureState(context_t *context)
 						 bo,
 						 r700->textures[i]->SQ_TEX_RESOURCE3,
 						 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
 			    END_BATCH();
 
 			    BEGIN_BATCH_NO_AUTOSTATE(5);
@@ -362,22 +364,21 @@ void r700SetupVTXConstants(GLcontext  * ctx,
     SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
 	     SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
 
-    BEGIN_BATCH_NO_AUTOSTATE(9);
+    BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
 
     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
     R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
-
-    R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
-                         paos->bo,
-                         uSQ_VTX_CONSTANT_WORD0_0,
-                         RADEON_GEM_DOMAIN_GTT, 0, 0);
+    R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
     R600_OUT_BATCH(0);
     R600_OUT_BATCH(0);
     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
-
+    R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
+                         paos->bo,
+                         uSQ_VTX_CONSTANT_WORD0_0,
+                         RADEON_GEM_DOMAIN_GTT, 0, 0);
     END_BATCH();
     COMMIT_BATCH();
 
@@ -515,16 +516,17 @@ GLboolean r700SendDepthTargetState(context_t *context)
 		return GL_FALSE;
 	}
 
-        BEGIN_BATCH_NO_AUTOSTATE(8);
+        BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
 	R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
 	R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
 	R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
 	R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
+	R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
+	R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
 	R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
 			     rrb->bo,
 			     r700->DB_DEPTH_BASE.u32All,
 			     0, RADEON_GEM_DOMAIN_VRAM, 0);
-	R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
         END_BATCH();
 
 	if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
@@ -561,8 +563,9 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
 	if (!r700->render_target[id].enabled)
 		return GL_FALSE;
 
-        BEGIN_BATCH_NO_AUTOSTATE(3);
+        BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 	R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
+	R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All);
 	R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
 			     rrb->bo,
 			     r700->render_target[id].CB_COLOR0_BASE.u32All,
@@ -607,8 +610,9 @@ GLboolean r700SendPSState(context_t *context)
 
 	r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 
-        BEGIN_BATCH_NO_AUTOSTATE(3);
+        BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 	R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
+	R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
 	R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
 			     pbo,
 			     r700->ps.SQ_PGM_START_PS.u32All,
@@ -639,8 +643,9 @@ GLboolean r700SendVSState(context_t *context)
 
 	r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 
-        BEGIN_BATCH_NO_AUTOSTATE(3);
+        BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 	R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
+	R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
 	R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
 			     pbo,
 			     r700->vs.SQ_PGM_START_VS.u32All,
@@ -679,8 +684,9 @@ GLboolean r700SendFSState(context_t *context)
 
 	r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 
-        BEGIN_BATCH_NO_AUTOSTATE(3);
+        BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 	R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
+	R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
 	R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
 			     pbo,
 			     r700->fs.SQ_PGM_START_FS.u32All,
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 6985bd4ffa..58b4491d00 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -166,15 +166,16 @@ GLboolean r700SyncSurf(context_t *context,
     else
 	    cp_coher_size = ((pbo->size + 255) >> 8);
 
-    BEGIN_BATCH_NO_AUTOSTATE(5);
+    BEGIN_BATCH_NO_AUTOSTATE(5 + 2);
     R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
     R600_OUT_BATCH(sync_type);
     R600_OUT_BATCH(cp_coher_size);
+    R600_OUT_BATCH(0);
+    R600_OUT_BATCH(10);
     R600_OUT_BATCH_RELOC(0,
 			 pbo,
 			 0,
 			 read_domain, write_domain, 0); // ???
-    R600_OUT_BATCH(10);
 
     END_BATCH();
     COMMIT_BATCH();