summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorChia-I Wu <olvaffe@gmail.com>2010-10-12 13:39:03 -0400
committerChia-I Wu <olvaffe@gmail.com>2011-03-16 20:18:39 +0800
commit5d1e2165f793807decbe51f239341fb1983e8cb4 (patch)
tree78d9b69553c8654ef567404ec249ed1b1122f6e2
parent39d10943012c2ba51cc12041faf6563eee7cb4a6 (diff)
android: Fix depth/stencil with i915c/i965c.
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index a5334f8367..7c422c4c3a 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -420,6 +420,32 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
}
}
+#ifdef ANDROID
+ depth_rb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
+ stencil_rb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
+ rb = NULL;
+ if (depth_rb && !depth_rb->region)
+ rb = depth_rb;
+ else if (stencil_rb && !stencil_rb->region)
+ rb = stencil_rb;
+ if (rb) {
+ uint32_t tiling = I915_TILING_NONE;
+
+ /* Gen6 requires depth must be tiling */
+ if (intel->gen >= 6 && rb->Base.Format == MESA_FORMAT_S8_Z24)
+ tiling = I915_TILING_Y;
+
+ region = intel_region_alloc(intel->intelScreen, tiling,
+ _mesa_get_format_bytes(rb->Base.Format),
+ drawable->w, drawable->h, GL_TRUE);
+ intel_renderbuffer_set_region(intel, rb, region);
+ intel_region_release(&region);
+ }
+
+ if (stencil_rb && !stencil_rb->region)
+ intel_renderbuffer_set_region(intel, stencil_rb, depth_rb->region);
+#endif
+
driUpdateFramebufferSize(&intel->ctx, drawable);
}