diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-17 14:25:43 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-28 15:58:20 +0800 |
| commit | a0b1d7b2b8d35f30793d811d7b5a693e9ea17596 (patch) | |
| tree | 7d5163f174db2e3883416bce4dda4ee91e365beb | |
| parent | 67dafa4b56422b44ca26b093d8feb6e743eb89e6 (diff) | |
i965: ignore quads for GS kernel on sandybridge
Sandybridge's VF would convert quads to polygon which not required
for GS then. Current GS state still would cause hang on lineloop.
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index 5409e55788..8952c9e346 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -60,7 +60,7 @@ static void compile_gs_prog( struct brw_context *brw, */ c.nr_attrs = brw_count_bits(c.key.attrs); - if (intel->gen == 5) + if (intel->gen >= 5) c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */ else c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */ @@ -85,12 +85,19 @@ static void compile_gs_prog( struct brw_context *brw, */ switch (key->primitive) { case GL_QUADS: + /* Gen6: VF has already converted into polygon. */ + if (intel->gen == 6) + return; brw_gs_quads( &c, key ); break; case GL_QUAD_STRIP: + if (intel->gen == 6) + return; brw_gs_quad_strip( &c, key ); break; case GL_LINE_LOOP: + /* XXX fix GS hang issue */ + assert(intel->gen < 6); brw_gs_lines( &c ); break; case GL_LINES: |