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authorEric Anholt <eric@anholt.net>2009-08-18 18:48:54 -0700
committerEric Anholt <eric@anholt.net>2009-08-19 09:19:06 -0700
commita70e1315846cd5e8d6f2b622821ff8262fe7179d (patch)
tree1b1fe01f554aaf6f737cd6b6023edd10b85b404c
parentb053474378633249be0e9f24010650ffb816229a (diff)
intel: Align cubemap texture height to its padding requirements.
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 1d2e953eb1..5e4f7fd27b 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -194,6 +194,16 @@ GLboolean brw_miptree_layout(struct intel_context *intel,
}
}
+ /* The 965's sampler lays cachelines out according to how accesses
+ * in the texture surfaces run, so they may be "vertical" through
+ * memory. As a result, the docs say in Surface Padding Requirements:
+ * Sampling Engine Surfaces that two extra rows of padding are required.
+ * We don't know of similar requirements for pre-965, but given that
+ * those docs are silent on padding requirements in general, let's play
+ * it safe.
+ */
+ if (mt->target == GL_TEXTURE_CUBE_MAP)
+ total_height += 2;
break;
}