diff options
| author | Eric Anholt <eric@anholt.net> | 2010-03-27 13:01:51 -0700 |
|---|---|---|
| committer | Ian Romanick <ian.d.romanick@intel.com> | 2010-03-29 12:48:45 -0700 |
| commit | 44d68fd06ff8b53fc70a9a07c897dda9b3457ef8 (patch) | |
| tree | b01b0d1c2c631a3539509e117569d1d9f9f57171 /builtin_function.cpp | |
| parent | ddd2e83db2b6baa062f76f22bb980030144dbcad (diff) | |
Add sqrt() builtin as an IR operation.
Following a discussion in #dri-devel, I think this makes more sense
than implementing it as RSQ RCP CMP as Mesa did. The i965 has a
hardware sqrt that should work, and AMD is suppposed to be able to
implement it as RSQ RCP with an alternate floating point mode so that
the 0.0 case is handled like we want.
Diffstat (limited to 'builtin_function.cpp')
| -rw-r--r-- | builtin_function.cpp | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/builtin_function.cpp b/builtin_function.cpp index ec1b54a2dd..9d231e872b 100644 --- a/builtin_function.cpp +++ b/builtin_function.cpp @@ -85,6 +85,14 @@ generate_rsq(exec_list *instructions, } static void +generate_sqrt(exec_list *instructions, + ir_variable **declarations, + const glsl_type *type) +{ + generate_unop(instructions, declarations, type, ir_unop_sqrt); +} + +static void generate_abs(exec_list *instructions, ir_variable **declarations, const glsl_type *type) @@ -227,7 +235,7 @@ generate_110_functions(glsl_symbol_table *symtab, exec_list *instructions) make_gentype_function(symtab, instructions, "log", 1, generate_log); /* FINISHME: exp2() */ /* FINISHME: log2() */ - /* FINISHME: sqrt() */ + make_gentype_function(symtab, instructions, "sqrt", 1, generate_sqrt); make_gentype_function(symtab, instructions, "inversesqrt", 1, generate_rsq); make_gentype_function(symtab, instructions, "abs", 1, generate_abs); /* FINISHME: sign() */ |