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| author | Eric Anholt <eric@anholt.net> | 2010-10-26 14:36:18 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-10-26 15:07:10 -0700 |
| commit | 00bfdac5b8e20463c04b9ec3f67bf1392fb86205 (patch) | |
| tree | 7db0665cf14181ddc4d5f58bed08cb22a3390b3e /common.py | |
| parent | 88087ba1bf5566c8fe1c7d88028d2485126af286 (diff) | |
i965: Fix VS URB entry sizing.
I'm trying to clamp to a minimum of 1 URB row, not a maximum of 1.
Fixes:
glsl-kwin-blur
glsl-max-varying
glsl-routing
Diffstat (limited to 'common.py')
0 files changed, 0 insertions, 0 deletions