diff options
author | Keith Whitwell <keith@tungstengraphics.com> | 2008-09-11 18:32:05 +0100 |
---|---|---|
committer | Keith Whitwell <keith@tungstengraphics.com> | 2008-09-11 18:32:05 +0100 |
commit | cc7dd4fc1b3c765ca1ecd943d189bb156dae529d (patch) | |
tree | 1a3560eb6df8a443c4f0e5af0a916f190b1542f6 /src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h | |
parent | 685248bea1fef5fd6335982570e34d0f6672030d (diff) | |
parent | d50d68a1c940ed9c8d8c65e8e33667fa90d5baa1 (diff) |
Merge commit 'origin/gallium-0.1' into gallium-0.2
Conflicts:
Makefile
progs/demos/Makefile
progs/glsl/Makefile
progs/redbook/Makefile
progs/samples/Makefile
progs/tests/Makefile
progs/trivial/Makefile
progs/xdemos/Makefile
src/gallium/Makefile
src/mesa/main/attrib.c
src/mesa/main/bufferobj.c
src/mesa/vbo/vbo_exec_draw.c
Diffstat (limited to 'src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h')
-rw-r--r-- | src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h | 52 |
1 files changed, 43 insertions, 9 deletions
diff --git a/src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h b/src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h index 1cacc717b1..dee8c55c4a 100644 --- a/src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h +++ b/src/gallium/auxiliary/rtasm/rtasm_ppc_spe.h @@ -25,6 +25,7 @@ /** * \file * Real-time assembly generation interface for Cell B.E. SPEs. + * For details, see /opt/cell/sdk/docs/arch/SPU_ISA_v1.2_27Jan2007_pub.pdf * * \author Ian Romanick <idr@us.ibm.com> */ @@ -32,13 +33,24 @@ #ifndef RTASM_PPC_SPE_H #define RTASM_PPC_SPE_H -struct spe_function { - /** - * - */ - uint32_t *store; - uint32_t *csr; - const char *fn; +/** 4 bytes per instruction */ +#define SPE_INST_SIZE 4 + +/** number of general-purpose SIMD registers */ +#define SPE_NUM_REGS 128 + +/** Return Address register */ +#define SPE_REG_RA 0 + +/** Stack Pointer register */ +#define SPE_REG_SP 1 + + +struct spe_function +{ + uint32_t *store; /**< instruction buffer */ + uint num_inst; + uint max_inst; /** * Mask of used / unused registers @@ -50,7 +62,7 @@ struct spe_function { * spe_allocate_register, spe_allocate_available_register, * spe_release_register */ - uint64_t regs[2]; + uint64_t regs[SPE_NUM_REGS / 64]; }; extern void spe_init_func(struct spe_function *p, unsigned code_size); @@ -119,7 +131,8 @@ EMIT_RI16(spe_ilhu, 0x082); EMIT_RI16(spe_il, 0x081); EMIT_RI18(spe_ila, 0x021); EMIT_RI16(spe_iohl, 0x0c1); -EMIT_RI16(spe_fsmbi, 0x0c5); +EMIT_RI16(spe_fsmbi, 0x065); + /* Integer and logical instructions @@ -271,6 +284,27 @@ extern void spe_bihnz(struct spe_function *p, unsigned rT, unsigned rA, int d, int e); +/** Load/splat immediate float into rT. */ +extern void +spe_load_float(struct spe_function *p, unsigned rT, float x); + +/** Load/splat immediate int into rT. */ +extern void +spe_load_int(struct spe_function *p, unsigned rT, int i); + +/** Complement/invert all bits in rT. */ +extern void +spe_complement(struct spe_function *p, unsigned rT); + +/** rT = rA. */ +extern void +spe_move(struct spe_function *p, unsigned rT, unsigned rA); + +/** rT = {0,0,0,0}. */ +extern void +spe_zero(struct spe_function *p, unsigned rT); + + /* Floating-point instructions */ EMIT_RR (spe_fa, 0x2c4); |