diff options
author | Zack Rusin <zackr@vmware.com> | 2010-06-18 13:41:20 -0400 |
---|---|---|
committer | Zack Rusin <zackr@vmware.com> | 2010-06-18 13:46:44 -0400 |
commit | 101f792a2af9c9a19a050afba8b60caa689466a5 (patch) | |
tree | d79405c3da0da947a90d70dc7670b03a9855b237 /src/gallium/auxiliary/tgsi/tgsi_parse.c | |
parent | 2b221e11da7a8bf759e3c359f22ba6f49d5f0997 (diff) |
gallium: add a temporary array register file
like normal temporaries, but allows to define a number of distinct
arrays, all of which make it explicit that they contain /indexable/
registers.
as a side-effect we're adding support for multi-dimensional destination
registers.
The whole thing looks like this:
DCL TEMPX[0][0..128] # 0 array with 128 registers
ADD TEMPX[0][0], IN[0], IMM[0]
ADD TEMPX[0][1], IN[0], IMM[0]
ABS OUT[0], TEMPX[0][TEMP[0]]
Diffstat (limited to 'src/gallium/auxiliary/tgsi/tgsi_parse.c')
-rw-r--r-- | src/gallium/auxiliary/tgsi/tgsi_parse.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/src/gallium/auxiliary/tgsi/tgsi_parse.c b/src/gallium/auxiliary/tgsi/tgsi_parse.c index ae8c868dcb..db9a342220 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_parse.c +++ b/src/gallium/auxiliary/tgsi/tgsi_parse.c @@ -192,11 +192,6 @@ tgsi_parse_token( next_token( ctx, &inst->Dst[i].Register ); - /* - * No support for indirect or multi-dimensional addressing. - */ - assert( !inst->Dst[i].Register.Dimension ); - if( inst->Dst[i].Register.Indirect ) { next_token( ctx, &inst->Dst[i].Indirect ); @@ -206,6 +201,24 @@ tgsi_parse_token( assert( !inst->Dst[i].Indirect.Dimension ); assert( !inst->Dst[i].Indirect.Indirect ); } + if( inst->Dst[i].Register.Dimension ) { + next_token( ctx, &inst->Dst[i].Dimension ); + + /* + * No support for multi-dimensional addressing. + */ + assert( !inst->Dst[i].Dimension.Dimension ); + + if( inst->Dst[i].Dimension.Indirect ) { + next_token( ctx, &inst->Dst[i].DimIndirect ); + + /* + * No support for indirect or multi-dimensional addressing. + */ + assert( !inst->Dst[i].Indirect.Indirect ); + assert( !inst->Dst[i].Indirect.Dimension ); + } + } } assert( inst->Instruction.NumSrcRegs <= TGSI_FULL_MAX_SRC_REGISTERS ); |