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authorKeith Whitwell <keithw@vmware.com>2009-10-24 17:07:01 +0100
committerKeith Whitwell <keithw@vmware.com>2009-10-24 17:07:28 +0100
commit4f7931bb3554cb1839adc2044e3abe6d4af8b0b5 (patch)
tree46999bd594cd839f1ad58dc799bd721c4b45d35e /src/gallium/drivers/i965/brw_reg.h
parent074606a806df755ecbb84e0a1182c66fd0b2a8dd (diff)
i965g: more work on compiling
Diffstat (limited to 'src/gallium/drivers/i965/brw_reg.h')
-rw-r--r--src/gallium/drivers/i965/brw_reg.h36
1 files changed, 36 insertions, 0 deletions
diff --git a/src/gallium/drivers/i965/brw_reg.h b/src/gallium/drivers/i965/brw_reg.h
index a640104d71..f428ec9269 100644
--- a/src/gallium/drivers/i965/brw_reg.h
+++ b/src/gallium/drivers/i965/brw_reg.h
@@ -76,4 +76,40 @@
#define FENCE_YMAJOR 2
+
+/* PCI IDs
+ */
+#define PCI_CHIP_I965_G 0x29A2
+#define PCI_CHIP_I965_Q 0x2992
+#define PCI_CHIP_I965_G_1 0x2982
+#define PCI_CHIP_I946_GZ 0x2972
+#define PCI_CHIP_I965_GM 0x2A02
+#define PCI_CHIP_I965_GME 0x2A12
+
+#define PCI_CHIP_GM45_GM 0x2A42
+
+#define PCI_CHIP_IGD_E_G 0x2E02
+#define PCI_CHIP_Q45_G 0x2E12
+#define PCI_CHIP_G45_G 0x2E22
+#define PCI_CHIP_G41_G 0x2E32
+#define PCI_CHIP_B43_G 0x2E42
+
+#define PCI_CHIP_ILD_G 0x0042
+#define PCI_CHIP_ILM_G 0x0046
+
+struct brw_chipset {
+ int pci_id:16;
+ int is_965:1;
+ int is_igdng:1;
+ int is_g4x:1;
+ int pad:13;
+};
+
+
+/* XXX: hacks
+ */
+#define VERT_RESULT_HPOS 0 /* not always true */
+#define VERT_RESULT_PSIZ 10000 /* disabled */
+
+
#endif