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authorKeith Whitwell <keithw@vmware.com>2009-10-31 18:23:14 +0000
committerKeith Whitwell <keithw@vmware.com>2009-10-31 18:23:14 +0000
commitf202a34cb1eca41cf5d12bd72016f284bc81ccf8 (patch)
tree73f3ba8cb1240706edf75808e362e611bfbe54d6 /src/gallium/drivers/i965/brw_wm.h
parent5d61b6f1f64ca26dd038af0679873ef0353660dd (diff)
i965g: non-glsl fragment shader path is compiling
Disabled glsl code for now, probably want to clean this up somehow.
Diffstat (limited to 'src/gallium/drivers/i965/brw_wm.h')
-rw-r--r--src/gallium/drivers/i965/brw_wm.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/gallium/drivers/i965/brw_wm.h b/src/gallium/drivers/i965/brw_wm.h
index 8ee99420aa..48dac39756 100644
--- a/src/gallium/drivers/i965/brw_wm.h
+++ b/src/gallium/drivers/i965/brw_wm.h
@@ -56,9 +56,6 @@
#define AA_ALWAYS 2
struct brw_wm_prog_key {
- unsigned proj_attrib_mask; /**< one bit per fragment program attribute */
- unsigned linear_attrib_mask; /**< linear interpolation vs perspective interp */
-
GLuint source_depth_reg:3;
GLuint aa_dest_stencil_reg:3;
GLuint dest_depth_reg:3;
@@ -73,6 +70,7 @@ struct brw_wm_prog_key {
GLuint yuvtex_swap_mask:16; /* UV swaped */
GLuint vp_nr_outputs:6;
+ GLuint nr_inputs:6;
GLuint nr_cbufs:3;
GLuint has_flow_control:1;
@@ -179,6 +177,12 @@ struct brw_wm_instruction {
#define BRW_FILE_PAYLOAD (TGSI_FILE_COUNT)
#define PAYLOAD_DEPTH (PIPE_MAX_SHADER_INPUTS) /* ?? */
+#define X 0
+#define Y 1
+#define Z 2
+#define W 3
+#define GET_SWZ(swz, comp) (((swz) >> ((comp)*2)) & 0x3)
+
struct brw_fp_src {
unsigned file:4;