nvc0: port to common fence/mm/buffer code

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 6 insertions, 139 deletions

diff --git a/src/gallium/drivers/nvc0/nvc0_resource.h b/src/gallium/drivers/nvc0/nvc0_resource.h
index 599823c0dc..7821db51b7 100644
--- a/src/gallium/drivers/nvc0/nvc0_resource.h
+++ b/src/gallium/drivers/nvc0/nvc0_resource.h
@@ -6,115 +6,15 @@
 #include "util/u_double_list.h"
 #define NOUVEAU_NVC0
 #include "nouveau/nouveau_winsys.h"
+#include "nouveau/nouveau_fence.h"
+#include "nouveau/nouveau_buffer.h"
 #undef NOUVEAU_NVC0
 
-#include "nvc0_fence.h"
-
-struct pipe_resource;
-struct nouveau_bo;
-struct nvc0_context;
-
-#define NVC0_BUFFER_SCORE_MIN -25000
-#define NVC0_BUFFER_SCORE_MAX  25000
-#define NVC0_BUFFER_SCORE_VRAM_THRESHOLD 20000
-
-/* DIRTY: buffer was (or will be after the next flush) written to by GPU and
- *  resource->data has not been updated to reflect modified VRAM contents
- *
- * USER_MEMORY: resource->data is a pointer to client memory and may change
- *  between GL calls
- */
-#define NVC0_BUFFER_STATUS_GPU_READING (1 << 0)
-#define NVC0_BUFFER_STATUS_GPU_WRITING (1 << 1)
-#define NVC0_BUFFER_STATUS_USER_MEMORY (1 << 7)
-
-/* Resources, if mapped into the GPU's address space, are guaranteed to
- * have constant virtual addresses.
- * The address of a resource will lie within the nouveau_bo referenced,
- * and this bo should be added to the memory manager's validation list.
- */
-struct nvc0_resource {
-   struct pipe_resource base;
-   const struct u_resource_vtbl *vtbl;
-
-   uint8_t *data;
-   struct nouveau_bo *bo;
-   uint32_t offset;
-
-   uint8_t status;
-   uint8_t domain;
-
-   int16_t score; /* low if mapped very often, if high can move to VRAM */
-
-   struct nvc0_fence *fence;
-   struct nvc0_fence *fence_wr;
-
-   struct nvc0_mm_allocation *mm;
-};
-
 void
-nvc0_buffer_release_gpu_storage(struct nvc0_resource *);
-
-boolean
-nvc0_buffer_download(struct nvc0_context *, struct nvc0_resource *,
-                     unsigned start, unsigned size);
-
-boolean
-nvc0_buffer_migrate(struct nvc0_context *,
-                    struct nvc0_resource *, unsigned domain);
-
-static INLINE void
-nvc0_buffer_adjust_score(struct nvc0_context *nvc0, struct nvc0_resource *res,
-                         int16_t score)
-{
-   if (score < 0) {
-      if (res->score > NVC0_BUFFER_SCORE_MIN)
-         res->score += score;
-   } else
-   if (score > 0){
-      if (res->score < NVC0_BUFFER_SCORE_MAX)
-         res->score += score;
-      if (res->domain == NOUVEAU_BO_GART &&
-          res->score > NVC0_BUFFER_SCORE_VRAM_THRESHOLD)
-         nvc0_buffer_migrate(nvc0, res, NOUVEAU_BO_VRAM);
-   }
-}
-
-/* XXX: wait for fence (atm only using this for vertex push) */
-static INLINE void *
-nvc0_resource_map_offset(struct nvc0_context *nvc0,
-                         struct nvc0_resource *res, uint32_t offset,
-                         uint32_t flags)
-{
-   void *map;
-
-   nvc0_buffer_adjust_score(nvc0, res, -250);
-
-   if ((res->domain == NOUVEAU_BO_VRAM) &&
-       (res->status & NVC0_BUFFER_STATUS_GPU_WRITING))
-      nvc0_buffer_download(nvc0, res, 0, res->base.width0);
-
-   if ((res->domain != NOUVEAU_BO_GART) ||
-       (res->status & NVC0_BUFFER_STATUS_USER_MEMORY))
-      return res->data + offset;
-
-   if (res->mm)
-      flags |= NOUVEAU_BO_NOSYNC;
-
-   if (nouveau_bo_map_range(res->bo, res->offset + offset,
-                            res->base.width0, flags))
-      return NULL;
-
-   map = res->bo->map;
-   nouveau_bo_unmap(res->bo);
-   return map;
-}
+nvc0_init_resource_functions(struct pipe_context *pcontext);
 
-static INLINE void
-nvc0_resource_unmap(struct nvc0_resource *res)
-{
-   /* no-op */
-}
+void
+nvc0_screen_init_resource_functions(struct pipe_screen *pscreen);
 
 #define NVC0_TILE_DIM_SHIFT(m, d) (((m) >> (d * 4)) & 0xf)
 
@@ -137,7 +37,7 @@ struct nvc0_miptree_level {
 #define NVC0_MAX_TEXTURE_LEVELS 16
 
 struct nvc0_miptree {
-   struct nvc0_resource base;
+   struct nv04_resource base;
    struct nvc0_miptree_level level[NVC0_MAX_TEXTURE_LEVELS];
    uint32_t total_size;
    uint32_t layer_stride;
@@ -150,25 +50,6 @@ nvc0_miptree(struct pipe_resource *pt)
    return (struct nvc0_miptree *)pt;
 }
 
-static INLINE struct nvc0_resource *
-nvc0_resource(struct pipe_resource *resource)
-{
-   return (struct nvc0_resource *)resource;
-}
-
-/* is resource mapped into the GPU's address space (i.e. VRAM or GART) ? */
-static INLINE boolean
-nvc0_resource_mapped_by_gpu(struct pipe_resource *resource)
-{
-   return nvc0_resource(resource)->domain != 0;
-}
-
-void
-nvc0_init_resource_functions(struct pipe_context *pcontext);
-
-void
-nvc0_screen_init_resource_functions(struct pipe_screen *pscreen);
-
 /* Internal functions:
  */
 struct pipe_resource *
@@ -180,17 +61,6 @@ nvc0_miptree_from_handle(struct pipe_screen *pscreen,
                          const struct pipe_resource *template,
                          struct winsys_handle *whandle);
 
-struct pipe_resource *
-nvc0_buffer_create(struct pipe_screen *pscreen,
-                   const struct pipe_resource *templ);
-
-struct pipe_resource *
-nvc0_user_buffer_create(struct pipe_screen *screen,
-                        void *ptr,
-                        unsigned bytes,
-                        unsigned usage);
-
-
 struct pipe_surface *
 nvc0_miptree_surface_new(struct pipe_context *,
                          struct pipe_resource *,
@@ -199,7 +69,4 @@ nvc0_miptree_surface_new(struct pipe_context *,
 void
 nvc0_miptree_surface_del(struct pipe_context *, struct pipe_surface *);
 
-boolean
-nvc0_user_buffer_upload(struct nvc0_resource *, unsigned base, unsigned size);
-
 #endif