r600g: initial evergreen support in new path

This doesn't work yet.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>

1 files changed, 410 insertions, 0 deletions

diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 77cd8f1588..1973da3647 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -26,6 +26,23 @@
 #ifndef EVERGREEND_H
 #define EVERGREEND_H
 
+/* evergreen values */
+#define EVERGREEN_CONFIG_REG_OFFSET                 0X00008000
+#define EVERGREEN_CONFIG_REG_END                    0X0000AC00
+#define EVERGREEN_CONTEXT_REG_OFFSET                0X00028000
+#define EVERGREEN_CONTEXT_REG_END                   0X00029000
+#define EVERGREEN_RESOURCE_OFFSET                   0x00030000
+#define EVERGREEN_RESOURCE_END                      0x00030400
+#define EVERGREEN_LOOP_CONST_OFFSET                 0x0003A200
+#define EVERGREEN_LOOP_CONST_END                    0x0003A26C
+#define EVERGREEN_BOOL_CONST_OFFSET                 0x0003A500
+#define EVERGREEN_BOOL_CONST_END                    0x0003A506
+#define EVERGREEN_SAMPLER_OFFSET                    0X0003C000
+#define EVERGREEN_SAMPLER_END                       0X0003CFF0
+
+#define EVENT_TYPE_ZPASS_DONE                  0x15
+#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
+
 #define R600_TEXEL_PITCH_ALIGNMENT_MASK        0x7
 
 #define PKT3_NOP                               0x10
@@ -1456,4 +1473,397 @@
 #define SQ_TEX_INST_SAMPLE 0x10
 #define SQ_TEX_INST_SAMPLE_L 0x11
 #define SQ_TEX_INST_SAMPLE_C 0x18
+
+#define R_008A14_PA_CL_ENHANCE                       0x00008A14
+#define R_008C0C_SQ_THREAD_RESOURCE_MGMT             0x00008C0C
+#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ        0x00008D8C
+#define R_028000_DB_RENDER_CONTROL                   0x00028000
+#define R_028008_DB_DEPTH_VIEW                       0x00028008
+#define R_02800C_DB_RENDER_OVERRIDE                  0x0002800C
+#define R_028010_DB_RENDER_OVERRIDE2                 0x00028010
+#define R_028014_DB_HTILE_DATA_BASE                  0x00028014
+#define R_028028_DB_STENCIL_CLEAR                    0x00028028
+#define R_02802C_DB_DEPTH_CLEAR                      0x0002802C
+#define R_028048_DB_Z_READ_BASE                      0x00028048
+#define R_02804C_DB_STENCIL_READ_BASE                0x0002804C
+#define R_028050_DB_Z_WRITE_BASE                     0x00028050
+#define R_028054_DB_STENCIL_WRITE_BASE               0x00028054
+#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0          0x00028140
+#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0          0x00028180
+#define R_028200_PA_SC_WINDOW_OFFSET                 0x00028200
+#define R_02820C_PA_SC_CLIPRECT_RULE                 0x0002820C
+#define R_028210_PA_SC_CLIPRECT_0_TL                 0x00028210
+#define R_028214_PA_SC_CLIPRECT_0_BR                 0x00028214
+#define R_028218_PA_SC_CLIPRECT_1_TL                 0x00028218
+#define R_02821C_PA_SC_CLIPRECT_1_BR                 0x0002821C
+#define R_028220_PA_SC_CLIPRECT_2_TL                 0x00028220
+#define R_028224_PA_SC_CLIPRECT_2_BR                 0x00028224
+#define R_028228_PA_SC_CLIPRECT_3_TL                 0x00028228
+#define R_02822C_PA_SC_CLIPRECT_3_BR                 0x0002822C
+#define R_028230_PA_SC_EDGERULE                      0x00028230
+#define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET        0x00028234
+#define R_028238_CB_TARGET_MASK                      0x00028238
+#define R_02823C_CB_SHADER_MASK                      0x0002823C
+#define R_028250_PA_SC_VPORT_SCISSOR_0_TL            0x00028250
+#define R_028254_PA_SC_VPORT_SCISSOR_0_BR            0x00028254
+#define R_028350_SX_MISC                             0x00028350
+#define R_028380_SQ_VTX_SEMANTIC_0                   0x00028380
+#define R_028384_SQ_VTX_SEMANTIC_1                   0x00028384
+#define R_028388_SQ_VTX_SEMANTIC_2                   0x00028388
+#define R_02838C_SQ_VTX_SEMANTIC_3                   0x0002838C
+#define R_028390_SQ_VTX_SEMANTIC_4                   0x00028390
+#define R_028394_SQ_VTX_SEMANTIC_5                   0x00028394
+#define R_028398_SQ_VTX_SEMANTIC_6                   0x00028398
+#define R_02839C_SQ_VTX_SEMANTIC_7                   0x0002839C
+#define R_0283A0_SQ_VTX_SEMANTIC_8                   0x000283A0
+#define R_0283A4_SQ_VTX_SEMANTIC_9                   0x000283A4
+#define R_0283A8_SQ_VTX_SEMANTIC_10                  0x000283A8
+#define R_0283AC_SQ_VTX_SEMANTIC_11                  0x000283AC
+#define R_0283B0_SQ_VTX_SEMANTIC_12                  0x000283B0
+#define R_0283B4_SQ_VTX_SEMANTIC_13                  0x000283B4
+#define R_0283B8_SQ_VTX_SEMANTIC_14                  0x000283B8
+#define R_0283BC_SQ_VTX_SEMANTIC_15                  0x000283BC
+#define R_0283C0_SQ_VTX_SEMANTIC_16                  0x000283C0
+#define R_0283C4_SQ_VTX_SEMANTIC_17                  0x000283C4
+#define R_0283C8_SQ_VTX_SEMANTIC_18                  0x000283C8
+#define R_0283CC_SQ_VTX_SEMANTIC_19                  0x000283CC
+#define R_0283D0_SQ_VTX_SEMANTIC_20                  0x000283D0
+#define R_0283D4_SQ_VTX_SEMANTIC_21                  0x000283D4
+#define R_0283D8_SQ_VTX_SEMANTIC_22                  0x000283D8
+#define R_0283DC_SQ_VTX_SEMANTIC_23                  0x000283DC
+#define R_0283E0_SQ_VTX_SEMANTIC_24                  0x000283E0
+#define R_0283E4_SQ_VTX_SEMANTIC_25                  0x000283E4
+#define R_0283E8_SQ_VTX_SEMANTIC_26                  0x000283E8
+#define R_0283EC_SQ_VTX_SEMANTIC_27                  0x000283EC
+#define R_0283F0_SQ_VTX_SEMANTIC_28                  0x000283F0
+#define R_0283F4_SQ_VTX_SEMANTIC_29                  0x000283F4
+#define R_0283F8_SQ_VTX_SEMANTIC_30                  0x000283F8
+#define R_0283FC_SQ_VTX_SEMANTIC_31                  0x000283FC
+#define R_0282D0_PA_SC_VPORT_ZMIN_0                  0x000282D0
+#define R_0282D4_PA_SC_VPORT_ZMAX_0                  0x000282D4
+#define R_028400_VGT_MAX_VTX_INDX                    0x00028400
+#define R_028404_VGT_MIN_VTX_INDX                    0x00028404
+#define R_028408_VGT_INDX_OFFSET                     0x00028408
+#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX        0x0002840C
+#define R_028414_CB_BLEND_RED                        0x00028414
+#define R_028418_CB_BLEND_GREEN                      0x00028418
+#define R_02841C_CB_BLEND_BLUE                       0x0002841C
+#define R_028420_CB_BLEND_ALPHA                      0x00028420
+#define R_028438_SX_ALPHA_REF                        0x00028438
+#define R_02843C_PA_CL_VPORT_XSCALE_0                0x0002843C
+#define R_028440_PA_CL_VPORT_XOFFSET_0               0x00028440
+#define R_028444_PA_CL_VPORT_YSCALE_0                0x00028444
+#define R_028448_PA_CL_VPORT_YOFFSET_0               0x00028448
+#define R_02844C_PA_CL_VPORT_ZSCALE_0                0x0002844C
+#define R_028450_PA_CL_VPORT_ZOFFSET_0               0x00028450
+#define R_0285BC_PA_CL_UCP0_X                        0x000285BC
+#define R_0285C0_PA_CL_UCP0_Y                        0x000285C0
+#define R_0285C4_PA_CL_UCP0_Z                        0x000285C4
+#define R_0285C8_PA_CL_UCP0_W                        0x000285C8
+#define R_0285CC_PA_CL_UCP1_X                        0x000285CC
+#define R_0285D0_PA_CL_UCP1_Y                        0x000285D0
+#define R_0285D4_PA_CL_UCP1_Z                        0x000285D4
+#define R_0285D8_PA_CL_UCP1_W                        0x000285D8
+#define R_0285DC_PA_CL_UCP2_X                        0x000285DC
+#define R_0285E0_PA_CL_UCP2_Y                        0x000285E0
+#define R_0285E4_PA_CL_UCP2_Z                        0x000285E4
+#define R_0285E8_PA_CL_UCP2_W                        0x000285E8
+#define R_0285EC_PA_CL_UCP3_X                        0x000285EC
+#define R_0285F0_PA_CL_UCP3_Y                        0x000285F0
+#define R_0285F4_PA_CL_UCP3_Z                        0x000285F4
+#define R_0285F8_PA_CL_UCP3_W                        0x000285F8
+#define R_0285FC_PA_CL_UCP4_X                        0x000285FC
+#define R_028600_PA_CL_UCP4_Y                        0x00028600
+#define R_028604_PA_CL_UCP4_Z                        0x00028604
+#define R_028608_PA_CL_UCP4_W                        0x00028608
+#define R_02860C_PA_CL_UCP5_X                        0x0002860C
+#define R_028610_PA_CL_UCP5_Y                        0x00028610
+#define R_028614_PA_CL_UCP5_Z                        0x00028614
+#define R_028618_PA_CL_UCP5_W                        0x00028618
+#define R_02861C_SPI_VS_OUT_ID_0                     0x0002861C
+#define R_028620_SPI_VS_OUT_ID_1                     0x00028620
+#define R_028624_SPI_VS_OUT_ID_2                     0x00028624
+#define R_028628_SPI_VS_OUT_ID_3                     0x00028628
+#define R_02862C_SPI_VS_OUT_ID_4                     0x0002862C
+#define R_028630_SPI_VS_OUT_ID_5                     0x00028630
+#define R_028634_SPI_VS_OUT_ID_6                     0x00028634
+#define R_028638_SPI_VS_OUT_ID_7                     0x00028638
+#define R_02863C_SPI_VS_OUT_ID_8                     0x0002863C
+#define R_028640_SPI_VS_OUT_ID_9                     0x00028640
+#define R_028648_SPI_PS_INPUT_CNTL_1                 0x00028648
+#define R_02864C_SPI_PS_INPUT_CNTL_2                 0x0002864C
+#define R_028650_SPI_PS_INPUT_CNTL_3                 0x00028650
+#define R_028654_SPI_PS_INPUT_CNTL_4                 0x00028654
+#define R_028658_SPI_PS_INPUT_CNTL_5                 0x00028658
+#define R_02865C_SPI_PS_INPUT_CNTL_6                 0x0002865C
+#define R_028660_SPI_PS_INPUT_CNTL_7                 0x00028660
+#define R_028664_SPI_PS_INPUT_CNTL_8                 0x00028664
+#define R_028668_SPI_PS_INPUT_CNTL_9                 0x00028668
+#define R_02866C_SPI_PS_INPUT_CNTL_10                0x0002866C
+#define R_028670_SPI_PS_INPUT_CNTL_11                0x00028670
+#define R_028674_SPI_PS_INPUT_CNTL_12                0x00028674
+#define R_028678_SPI_PS_INPUT_CNTL_13                0x00028678
+#define R_02867C_SPI_PS_INPUT_CNTL_14                0x0002867C
+#define R_028680_SPI_PS_INPUT_CNTL_15                0x00028680
+#define R_028684_SPI_PS_INPUT_CNTL_16                0x00028684
+#define R_028688_SPI_PS_INPUT_CNTL_17                0x00028688
+#define R_02868C_SPI_PS_INPUT_CNTL_18                0x0002868C
+#define R_028690_SPI_PS_INPUT_CNTL_19                0x00028690
+#define R_028694_SPI_PS_INPUT_CNTL_20                0x00028694
+#define R_028698_SPI_PS_INPUT_CNTL_21                0x00028698
+#define R_02869C_SPI_PS_INPUT_CNTL_22                0x0002869C
+#define R_0286A0_SPI_PS_INPUT_CNTL_23                0x000286A0
+#define R_0286A4_SPI_PS_INPUT_CNTL_24                0x000286A4
+#define R_0286A8_SPI_PS_INPUT_CNTL_25                0x000286A8
+#define R_0286AC_SPI_PS_INPUT_CNTL_26                0x000286AC
+#define R_0286B0_SPI_PS_INPUT_CNTL_27                0x000286B0
+#define R_0286B4_SPI_PS_INPUT_CNTL_28                0x000286B4
+#define R_0286B8_SPI_PS_INPUT_CNTL_29                0x000286B8
+#define R_0286BC_SPI_PS_INPUT_CNTL_30                0x000286BC
+#define R_0286C0_SPI_PS_INPUT_CNTL_31                0x000286C0
+#define R_0286C8_SPI_THREAD_GROUPING                 0x000286C8
+#define R_0286D8_SPI_INPUT_Z                         0x000286D8
+#define R_0286DC_SPI_FOG_CNTL                        0x000286DC
+#define R_0286E4_SPI_PS_IN_CONTROL_2                 0x000286E4
+#define R_0286E8_SPI_COMPUTE_INPUT_CNTL              0x000286E8
+#define R_028780_CB_BLEND0_CONTROL                   0x00028780
+#define R_028784_CB_BLEND1_CONTROL                   0x00028784
+#define R_028788_CB_BLEND2_CONTROL                   0x00028788
+#define R_02878C_CB_BLEND3_CONTROL                   0x0002878C
+#define R_028790_CB_BLEND4_CONTROL                   0x00028790
+#define R_028794_CB_BLEND5_CONTROL                   0x00028794
+#define R_028798_CB_BLEND6_CONTROL                   0x00028798
+#define R_02879C_CB_BLEND7_CONTROL                   0x0002879C
+#define R_028818_PA_CL_VTE_CNTL                      0x00028818
+#define R_028820_PA_CL_NANINF_CNTL                   0x00028820
+#define R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1         0x00028838
+#define R_028840_SQ_PGM_START_PS                     0x00028840
+#define R_02884C_SQ_PGM_EXPORTS_PS                   0x0002884C
+#define   S_02884C_EXPORT_COLORS(x)                    (((x) & 0xF) << 1)
+#define   G_02884C_EXPORT_COLORS(x)                    (((x) >> 1) & 0xF)
+#define   C_02884C_EXPORT_COLORS                       0xFFFFFFE1
+#define   S_02884C_EXPORT_Z(x)                         (((x) & 0x1) << 0)
+#define   G_02884C_EXPORT_Z(x)                         (((x) >> 0) & 0x1)
+#define   C_02884C_EXPORT_Z                            0xFFFFFFFE
+#define R_02885C_SQ_PGM_START_VS                     0x0002885C
+#define R_0288A4_SQ_PGM_START_FS                     0x000288A4
+#define R_0288A8_SQ_PGM_RESOURCES_FS                 0x000288A8
+#define R_0288EC_SQ_LDS_ALLOC_PS                     0x000288EC
+#define R_028900_SQ_ESGS_RING_ITEMSIZE               0x00028900
+#define R_028904_SQ_GSVS_RING_ITEMSIZE               0x00028904
+#define R_028908_SQ_ESTMP_RING_ITEMSIZE              0x00028908
+#define R_02890C_SQ_GSTMP_RING_ITEMSIZE              0x0002890C
+#define R_028910_SQ_VSTMP_RING_ITEMSIZE              0x00028910
+#define R_028914_SQ_PSTMP_RING_ITEMSIZE              0x00028914
+#define R_02891C_SQ_GS_VERT_ITEMSIZE                 0x0002891C
+#define R_028920_SQ_GS_VERT_ITEMSIZE_1               0x00028920
+#define R_028924_SQ_GS_VERT_ITEMSIZE_2               0x00028924
+#define R_028928_SQ_GS_VERT_ITEMSIZE_3               0x00028928
+#define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
+#define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
+#define R_028A04_PA_SU_POINT_MINMAX                  0x00028A04
+#define R_028A08_PA_SU_LINE_CNTL                     0x00028A08
+#define R_028A10_VGT_OUTPUT_PATH_CNTL                0x00028A10
+#define R_028A14_VGT_HOS_CNTL                        0x00028A14
+#define R_028A18_VGT_HOS_MAX_TESS_LEVEL              0x00028A18
+#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL              0x00028A1C
+#define R_028A20_VGT_HOS_REUSE_DEPTH                 0x00028A20
+#define R_028A24_VGT_GROUP_PRIM_TYPE                 0x00028A24
+#define R_028A28_VGT_GROUP_FIRST_DECR                0x00028A28
+#define R_028A2C_VGT_GROUP_DECR                      0x00028A2C
+#define R_028A30_VGT_GROUP_VECT_0_CNTL               0x00028A30
+#define R_028A34_VGT_GROUP_VECT_1_CNTL               0x00028A34
+#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL           0x00028A38
+#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL           0x00028A3C
+#define R_028A48_PA_SC_MODE_CNTL_0                   0x00028A48
+#define R_028A4C_PA_SC_MODE_CNTL_1                   0x00028A4C
+#define R_028AB4_VGT_REUSE_OFF                       0x00028AB4
+#define R_028AB8_VGT_VTX_CNT_EN                      0x00028AB8
+#define R_028ABC_DB_HTILE_SURFACE                    0x00028ABC
+#define R_028AC0_DB_SRESULTS_COMPARE_STATE0          0x00028AC0
+#define R_028AC4_DB_SRESULTS_COMPARE_STATE1          0x00028AC4
+#define R_028AC8_DB_PRELOAD_CONTROL                  0x00028AC8
+#define R_028B54_VGT_SHADER_STAGES_EN                0x00028B54
+#define R_028B70_DB_ALPHA_TO_MASK                    0x00028B70
+#define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x00028B78
+#define R_028B7C_PA_SU_POLY_OFFSET_CLAMP             0x00028B7C
+#define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE       0x00028B80
+#define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x00028B84
+#define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE        0x00028B88
+#define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x00028B8C
+#define R_028B94_VGT_STRMOUT_CONFIG                  0x00028B94
+#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG           0x00028B98
+#define R_028C00_PA_SC_LINE_CNTL                     0x00028C00
+#define R_028C04_PA_SC_AA_CONFIG                     0x00028C04
+#define R_028C08_PA_SU_VTX_CNTL                      0x00028C08
+#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ              0x00028C0C
+#define R_028C10_PA_CL_GB_VERT_DISC_ADJ              0x00028C10
+#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ              0x00028C14
+#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ              0x00028C18
+#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX           0x00028C1C
+#define R_028C3C_PA_SC_AA_MASK                       0x00028C3C
+#define R_028C60_CB_COLOR0_BASE                      0x00028C60
+#define R_028C6C_CB_COLOR0_VIEW                      0x00028C6C
+#define R_028C9C_CB_COLOR1_BASE                      0x00028C9C
+#define R_028CA0_CB_COLOR1_PITCH                     0x00028CA0
+#define R_028CA4_CB_COLOR1_SLICE                     0x00028CA4
+#define R_028CA8_CB_COLOR1_VIEW                      0x00028CA8
+#define R_028CAC_CB_COLOR1_INFO                      0x00028CAC
+#define R_028CB0_CB_COLOR1_ATTRIB                    0x00028CB0
+#define R_028CB8_CB_COLOR1_DIM                       0x00028CB8
+#define R_028CD8_CB_COLOR2_BASE                      0x00028CD8
+#define R_028CDC_CB_COLOR2_PITCH                     0x00028CDC
+#define R_028CE0_CB_COLOR2_SLICE                     0x00028CE0
+#define R_028CE4_CB_COLOR2_VIEW                      0x00028CE4
+#define R_028CE8_CB_COLOR2_INFO                      0x00028CE8
+#define R_028CEC_CB_COLOR2_ATTRIB                    0x00028CEC
+#define R_028CF0_CB_COLOR2_DIM                       0x00028CF0
+#define R_028D14_CB_COLOR3_BASE                      0x00028D14
+#define R_028D18_CB_COLOR3_PITCH                     0x00028D18
+#define R_028D1C_CB_COLOR3_SLICE                     0x00028D1C
+#define R_028D20_CB_COLOR3_VIEW                      0x00028D20
+#define R_028D24_CB_COLOR3_INFO                      0x00028D24
+#define R_028D28_CB_COLOR3_ATTRIB                    0x00028D28
+#define R_028D2C_CB_COLOR3_DIM                       0x00028D2C
+#define R_028D50_CB_COLOR4_BASE                      0x00028D50
+#define R_028D54_CB_COLOR4_PITCH                     0x00028D54
+#define R_028D58_CB_COLOR4_SLICE                     0x00028D58
+#define R_028D5C_CB_COLOR4_VIEW                      0x00028D5C
+#define R_028D60_CB_COLOR4_INFO                      0x00028D60
+#define R_028D64_CB_COLOR4_ATTRIB                    0x00028D64
+#define R_028D68_CB_COLOR4_DIM                       0x00028D68
+#define R_028D8C_CB_COLOR5_BASE                      0x00028D8C
+#define R_028D90_CB_COLOR5_PITCH                     0x00028D90
+#define R_028D94_CB_COLOR5_SLICE                     0x00028D94
+#define R_028D98_CB_COLOR5_VIEW                      0x00028D98
+#define R_028D9C_CB_COLOR5_INFO                      0x00028D9C
+#define R_028DA0_CB_COLOR5_ATTRIB                    0x00028DA0
+#define R_028DA4_CB_COLOR5_DIM                       0x00028DA4
+#define R_028DC8_CB_COLOR6_BASE                      0x00028DC8
+#define R_028DCC_CB_COLOR6_PITCH                     0x00028DCC
+#define R_028DD0_CB_COLOR6_SLICE                     0x00028DD0
+#define R_028DD4_CB_COLOR6_VIEW                      0x00028DD4
+#define R_028DD8_CB_COLOR6_INFO                      0x00028DD8
+#define R_028DDC_CB_COLOR6_ATTRIB                    0x00028DDC
+#define R_028DE0_CB_COLOR6_DIM                       0x00028DE0
+#define R_028E04_CB_COLOR7_BASE                      0x00028E04
+#define R_028E08_CB_COLOR7_PITCH                     0x00028E08
+#define R_028E0C_CB_COLOR7_SLICE                     0x00028E0C
+#define R_028E10_CB_COLOR7_VIEW                      0x00028E10
+#define R_028E14_CB_COLOR7_INFO                      0x00028E14
+#define R_028E18_CB_COLOR7_ATTRIB                    0x00028E18
+#define R_028E1C_CB_COLOR7_DIM                       0x00028E1C
+#define R_028E40_CB_COLOR8_BASE                      0x00028E40
+#define R_028E44_CB_COLOR8_PITCH                     0x00028E44
+#define R_028E48_CB_COLOR8_SLICE                     0x00028E48
+#define R_028E4C_CB_COLOR8_VIEW                      0x00028E4C
+#define R_028E50_CB_COLOR8_INFO                      0x00028E50
+#define R_028E54_CB_COLOR8_ATTRIB                    0x00028E54
+#define R_028E58_CB_COLOR8_DIM                       0x00028E58
+#define R_028E5C_CB_COLOR9_BASE                      0x00028E5C
+#define R_028E60_CB_COLOR9_PITCH                     0x00028E60
+#define R_028E64_CB_COLOR9_SLICE                     0x00028E64
+#define R_028E68_CB_COLOR9_VIEW                      0x00028E68
+#define R_028E6C_CB_COLOR9_INFO                      0x00028E6C
+#define R_028E70_CB_COLOR9_ATTRIB                    0x00028E70
+#define R_028E74_CB_COLOR9_DIM                       0x00028E74
+#define R_028E78_CB_COLOR10_BASE                     0x00028E78
+#define R_028E7C_CB_COLOR10_PITCH                    0x00028E7C
+#define R_028E80_CB_COLOR10_SLICE                    0x00028E80
+#define R_028E84_CB_COLOR10_VIEW                     0x00028E84
+#define R_028E88_CB_COLOR10_INFO                     0x00028E88
+#define R_028E8C_CB_COLOR10_ATTRIB                   0x00028E8C
+#define R_028E90_CB_COLOR10_DIM                      0x00028E90
+#define R_028E94_CB_COLOR11_BASE                     0x00028E94
+#define R_028E98_CB_COLOR11_PITCH                    0x00028E98
+#define R_028E9C_CB_COLOR11_SLICE                    0x00028E9C
+#define R_028EA0_CB_COLOR11_VIEW                     0x00028EA0
+#define R_028EA4_CB_COLOR11_INFO                     0x00028EA4
+#define R_028EA8_CB_COLOR11_ATTRIB                   0x00028EA8
+#define R_028EAC_CB_COLOR11_DIM                      0x00028EAC
+#define R_030000_RESOURCE0_WORD0                     0x00030000
+#define R_030004_RESOURCE0_WORD1                     0x00030004
+#define R_030008_RESOURCE0_WORD2                     0x00030008
+#define R_03000C_RESOURCE0_WORD3                     0x0003000C
+#define R_030010_RESOURCE0_WORD4                     0x00030010
+#define R_030014_RESOURCE0_WORD5                     0x00030014
+#define R_030018_RESOURCE0_WORD6                     0x00030018
+#define R_03001C_RESOURCE0_WORD7                     0x0003001C
+#define R_0085F0_CP_COHER_CNTL                       0x0085F0
+#define   S_0085F0_DEST_BASE_0_ENA(x)                  (((x) & 0x1) << 0)
+#define   G_0085F0_DEST_BASE_0_ENA(x)                  (((x) >> 0) & 0x1)
+#define   C_0085F0_DEST_BASE_0_ENA                     0xFFFFFFFE
+#define   S_0085F0_DEST_BASE_1_ENA(x)                  (((x) & 0x1) << 1)
+#define   G_0085F0_DEST_BASE_1_ENA(x)                  (((x) >> 1) & 0x1)
+#define   C_0085F0_DEST_BASE_1_ENA                     0xFFFFFFFD
+#define   S_0085F0_SO0_DEST_BASE_ENA(x)                (((x) & 0x1) << 2)
+#define   G_0085F0_SO0_DEST_BASE_ENA(x)                (((x) >> 2) & 0x1)
+#define   C_0085F0_SO0_DEST_BASE_ENA                   0xFFFFFFFB
+#define   S_0085F0_SO1_DEST_BASE_ENA(x)                (((x) & 0x1) << 3)
+#define   G_0085F0_SO1_DEST_BASE_ENA(x)                (((x) >> 3) & 0x1)
+#define   C_0085F0_SO1_DEST_BASE_ENA                   0xFFFFFFF7
+#define   S_0085F0_SO2_DEST_BASE_ENA(x)                (((x) & 0x1) << 4)
+#define   G_0085F0_SO2_DEST_BASE_ENA(x)                (((x) >> 4) & 0x1)
+#define   C_0085F0_SO2_DEST_BASE_ENA                   0xFFFFFFEF
+#define   S_0085F0_SO3_DEST_BASE_ENA(x)                (((x) & 0x1) << 5)
+#define   G_0085F0_SO3_DEST_BASE_ENA(x)                (((x) >> 5) & 0x1)
+#define   C_0085F0_SO3_DEST_BASE_ENA                   0xFFFFFFDF
+#define   S_0085F0_CB0_DEST_BASE_ENA(x)                (((x) & 0x1) << 6)
+#define   G_0085F0_CB0_DEST_BASE_ENA(x)                (((x) >> 6) & 0x1)
+#define   C_0085F0_CB0_DEST_BASE_ENA                   0xFFFFFFBF
+#define   S_0085F0_CB1_DEST_BASE_ENA(x)                (((x) & 0x1) << 7)
+#define   G_0085F0_CB1_DEST_BASE_ENA(x)                (((x) >> 7) & 0x1)
+#define   C_0085F0_CB1_DEST_BASE_ENA                   0xFFFFFF7F
+#define   S_0085F0_CB2_DEST_BASE_ENA(x)                (((x) & 0x1) << 8)
+#define   G_0085F0_CB2_DEST_BASE_ENA(x)                (((x) >> 8) & 0x1)
+#define   C_0085F0_CB2_DEST_BASE_ENA                   0xFFFFFEFF
+#define   S_0085F0_CB3_DEST_BASE_ENA(x)                (((x) & 0x1) << 9)
+#define   G_0085F0_CB3_DEST_BASE_ENA(x)                (((x) >> 9) & 0x1)
+#define   C_0085F0_CB3_DEST_BASE_ENA                   0xFFFFFDFF
+#define   S_0085F0_CB4_DEST_BASE_ENA(x)                (((x) & 0x1) << 10)
+#define   G_0085F0_CB4_DEST_BASE_ENA(x)                (((x) >> 10) & 0x1)
+#define   C_0085F0_CB4_DEST_BASE_ENA                   0xFFFFFBFF
+#define   S_0085F0_CB5_DEST_BASE_ENA(x)                (((x) & 0x1) << 11)
+#define   G_0085F0_CB5_DEST_BASE_ENA(x)                (((x) >> 11) & 0x1)
+#define   C_0085F0_CB5_DEST_BASE_ENA                   0xFFFFF7FF
+#define   S_0085F0_CB6_DEST_BASE_ENA(x)                (((x) & 0x1) << 12)
+#define   G_0085F0_CB6_DEST_BASE_ENA(x)                (((x) >> 12) & 0x1)
+#define   C_0085F0_CB6_DEST_BASE_ENA                   0xFFFFEFFF
+#define   S_0085F0_CB7_DEST_BASE_ENA(x)                (((x) & 0x1) << 13)
+#define   G_0085F0_CB7_DEST_BASE_ENA(x)                (((x) >> 13) & 0x1)
+#define   C_0085F0_CB7_DEST_BASE_ENA                   0xFFFFDFFF
+#define   S_0085F0_DB_DEST_BASE_ENA(x)                 (((x) & 0x1) << 14)
+#define   G_0085F0_DB_DEST_BASE_ENA(x)                 (((x) >> 14) & 0x1)
+#define   C_0085F0_DB_DEST_BASE_ENA                    0xFFFFBFFF
+#define   S_0085F0_CR_DEST_BASE_ENA(x)                 (((x) & 0x1) << 15)
+#define   G_0085F0_CR_DEST_BASE_ENA(x)                 (((x) >> 15) & 0x1)
+#define   C_0085F0_CR_DEST_BASE_ENA                    0xFFFF7FFF
+#define   S_0085F0_TC_ACTION_ENA(x)                    (((x) & 0x1) << 23)
+#define   G_0085F0_TC_ACTION_ENA(x)                    (((x) >> 23) & 0x1)
+#define   C_0085F0_TC_ACTION_ENA                       0xFF7FFFFF
+#define   S_0085F0_VC_ACTION_ENA(x)                    (((x) & 0x1) << 24)
+#define   G_0085F0_VC_ACTION_ENA(x)                    (((x) >> 24) & 0x1)
+#define   C_0085F0_VC_ACTION_ENA                       0xFEFFFFFF
+#define   S_0085F0_CB_ACTION_ENA(x)                    (((x) & 0x1) << 25)
+#define   G_0085F0_CB_ACTION_ENA(x)                    (((x) >> 25) & 0x1)
+#define   C_0085F0_CB_ACTION_ENA                       0xFDFFFFFF
+#define   S_0085F0_DB_ACTION_ENA(x)                    (((x) & 0x1) << 26)
+#define   G_0085F0_DB_ACTION_ENA(x)                    (((x) >> 26) & 0x1)
+#define   C_0085F0_DB_ACTION_ENA                       0xFBFFFFFF
+#define   S_0085F0_SH_ACTION_ENA(x)                    (((x) & 0x1) << 27)
+#define   G_0085F0_SH_ACTION_ENA(x)                    (((x) >> 27) & 0x1)
+#define   C_0085F0_SH_ACTION_ENA                       0xF7FFFFFF
+#define   S_0085F0_SMX_ACTION_ENA(x)                   (((x) & 0x1) << 28)
+#define   G_0085F0_SMX_ACTION_ENA(x)                   (((x) >> 28) & 0x1)
+#define   C_0085F0_SMX_ACTION_ENA                      0xEFFFFFFF
+#define   S_0085F0_CR0_ACTION_ENA(x)                   (((x) & 0x1) << 29)
+#define   G_0085F0_CR0_ACTION_ENA(x)                   (((x) >> 29) & 0x1)
+#define   C_0085F0_CR0_ACTION_ENA                      0xDFFFFFFF
+#define   S_0085F0_CR1_ACTION_ENA(x)                   (((x) & 0x1) << 30)
+#define   G_0085F0_CR1_ACTION_ENA(x)                   (((x) >> 30) & 0x1)
+#define   C_0085F0_CR1_ACTION_ENA                      0xBFFFFFFF
+#define   S_0085F0_CR2_ACTION_ENA(x)                   (((x) & 0x1) << 31)
+#define   G_0085F0_CR2_ACTION_ENA(x)                   (((x) >> 31) & 0x1)
+#define   C_0085F0_CR2_ACTION_ENA                      0x7FFFFFFF
+
 #endif