diff options
| author | Eric Anholt <eric@anholt.net> | 2010-07-26 17:47:59 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-07-26 17:53:27 -0700 |
| commit | afe125e0a18ac3886c45c7e6b02b122fb2d327b5 (patch) | |
| tree | 78621707e71154c0b388b0baacffc26432b7e992 /src/gallium/drivers/r600/r700_sq.h | |
| parent | d64343f1ae84979bd154475badf11af8a9bfc2eb (diff) | |
| parent | 5403ca79b225605c79f49866a6497c97da53be3b (diff) | |
Merge remote branch 'origin/master' into glsl2
This pulls in multiple i965 driver fixes which will help ensure better
testing coverage during development, and also gets past the conflicts
of the src/mesa/shader -> src/mesa/program move.
Conflicts:
src/mesa/Makefile
src/mesa/main/shaderapi.c
src/mesa/main/shaderobj.h
Diffstat (limited to 'src/gallium/drivers/r600/r700_sq.h')
| -rw-r--r-- | src/gallium/drivers/r600/r700_sq.h | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/gallium/drivers/r600/r700_sq.h b/src/gallium/drivers/r600/r700_sq.h index 8266af6d1f..9a117aeb1d 100644 --- a/src/gallium/drivers/r600/r700_sq.h +++ b/src/gallium/drivers/r600/r700_sq.h @@ -583,27 +583,5 @@ #define S_SQ_TEX_WORD2_SRC_SEL_W(x) (((x) & 0x7) << 29) #define G_SQ_TEX_WORD2_SRC_SEL_W(x) (((x) >> 29) & 0x7) #define C_SQ_TEX_WORD2_SRC_SEL_W 0x1FFFFFFF -#define P_SQ_ALU_WORD1_OP2_V2 -#define S_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x) (((x) & 0x1) << 0) -#define G_SQ_ALU_WORD1_OP2_V2_SRC0_ABS(x) (((x) >> 0) & 0x1) -#define C_SQ_ALU_WORD1_OP2_V2_SRC0_ABS 0xFFFFFFFE -#define S_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x) (((x) & 0x1) << 1) -#define G_SQ_ALU_WORD1_OP2_V2_SRC1_ABS(x) (((x) >> 1) & 0x1) -#define C_SQ_ALU_WORD1_OP2_V2_SRC1_ABS 0xFFFFFFFD -#define S_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x) (((x) & 0x1) << 2) -#define G_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK(x) (((x) >> 2) & 0x1) -#define C_SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK 0xFFFFFFFB -#define S_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x) (((x) & 0x1) << 3) -#define G_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED(x) (((x) >> 3) & 0x1) -#define C_SQ_ALU_WORD1_OP2_V2_UPDATE_PRED 0xFFFFFFF7 -#define S_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x) (((x) & 0x1) << 4) -#define G_SQ_ALU_WORD1_OP2_V2_WRITE_MASK(x) (((x) >> 4) & 0x1) -#define C_SQ_ALU_WORD1_OP2_V2_WRITE_MASK 0xFFFFFFEF -#define S_SQ_ALU_WORD1_OP2_V2_OMOD(x) (((x) & 0x3) << 5) -#define G_SQ_ALU_WORD1_OP2_V2_OMOD(x) (((x) >> 5) & 0x3) -#define C_SQ_ALU_WORD1_OP2_V2_OMOD 0xFFFFFF9F -#define S_SQ_ALU_WORD1_OP2_V2_ALU_INST(x) (((x) & 0x7FF) << 7) -#define G_SQ_ALU_WORD1_OP2_V2_ALU_INST(x) (((x) >> 7) & 0x7FF) -#define C_SQ_ALU_WORD1_OP2_V2_ALU_INST 0xFFFC007F #endif |