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authorMichel Dänzer <daenzer@vmware.com>2010-03-12 19:00:47 +0100
committerMichel Dänzer <daenzer@vmware.com>2010-03-12 19:00:47 +0100
commitb13e305ee1a2454265fd957a99640a2e49507bea (patch)
treee62dfd0ff761ec89de478499130d58d4b119aa0d /src/gallium/drivers
parentd1ca1599f0319f5c99852ce24420aa592e806db0 (diff)
parent8561bec0ac1ae5a8871c86f1f2cc29d44cb0f878 (diff)
Merge branch '7.8'
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/cell/ppu/cell_gen_fragment.c2
-rw-r--r--src/gallium/drivers/cell/ppu/cell_spu.c2
-rw-r--r--src/gallium/drivers/nv40/nv40_vertprog.c2
-rw-r--r--src/gallium/drivers/r300/r300_reg.h4
4 files changed, 5 insertions, 5 deletions
diff --git a/src/gallium/drivers/cell/ppu/cell_gen_fragment.c b/src/gallium/drivers/cell/ppu/cell_gen_fragment.c
index 576d514741..c54576b3c3 100644
--- a/src/gallium/drivers/cell/ppu/cell_gen_fragment.c
+++ b/src/gallium/drivers/cell/ppu/cell_gen_fragment.c
@@ -1352,7 +1352,7 @@ gen_stencil_values(struct spe_function *f,
*/
ASSERT(fbS_reg != newS_reg);
- /* The code also assumes the the stencil_max_value is of the form
+ /* The code also assumes that the stencil_max_value is of the form
* 2^n-1 and can therefore be used as a mask for the valid bits in
* addition to a maximum. Make sure this is the case as well.
* The clever math below exploits the fact that incrementing a
diff --git a/src/gallium/drivers/cell/ppu/cell_spu.c b/src/gallium/drivers/cell/ppu/cell_spu.c
index 28e5e6d706..39284f3a5d 100644
--- a/src/gallium/drivers/cell/ppu/cell_spu.c
+++ b/src/gallium/drivers/cell/ppu/cell_spu.c
@@ -135,7 +135,7 @@ cell_thread_function(void *arg)
/**
* Create the SPU threads. This is done once during driver initialization.
- * This involves setting the the "init" message which is sent to each SPU.
+ * This involves setting the "init" message which is sent to each SPU.
* The init message specifies an SPU id, total number of SPUs, location
* and number of batch buffers, etc.
*/
diff --git a/src/gallium/drivers/nv40/nv40_vertprog.c b/src/gallium/drivers/nv40/nv40_vertprog.c
index b289eef0fc..c93c5d127c 100644
--- a/src/gallium/drivers/nv40/nv40_vertprog.c
+++ b/src/gallium/drivers/nv40/nv40_vertprog.c
@@ -742,7 +742,7 @@ nv40_vertprog_translate(struct nv40_context *nv40,
}
/* Redirect post-transform vertex position to a temp if user clip
- * planes are enabled. We need to append code the the vtxprog
+ * planes are enabled. We need to append code to the vtxprog
* to handle clip planes later.
*/
if (vp->ucp.nr) {
diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h
index a249e8b36b..c67cc86871 100644
--- a/src/gallium/drivers/r300/r300_reg.h
+++ b/src/gallium/drivers/r300/r300_reg.h
@@ -540,7 +540,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_PVS_FIRST_INST(x) ((x) << 0)
# define R300_PVS_XYZW_VALID_INST(x) ((x) << 10)
# define R300_PVS_LAST_INST(x) ((x) << 20)
-/* Addresses are relative the the vertex program parameters area. */
+/* Addresses are relative to the vertex program parameters area. */
#define R300_VAP_PVS_CONST_CNTL 0x22D4
# define R300_PVS_CONST_BASE_OFFSET_SHIFT 0
# define R300_PVS_MAX_CONST_ADDR_SHIFT 16
@@ -1857,7 +1857,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* The destination register index is in FPI1 (color) and FPI3 (alpha)
* together with enable bits.
* There are separate enable bits for writing into temporary registers
- * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
+ * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_*
* /DSTA_OUTPUT). You can write to both at once, or not write at all (the
* same index must be used for both).
*