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authorEric Anholt <eric@anholt.net>2010-09-08 17:49:10 -0700
committerEric Anholt <eric@anholt.net>2010-09-08 18:05:22 -0700
commite04f90712d8e04ce9d2fee46d0cccf818432c7d9 (patch)
tree280343322dfd7136202a7cb8696d86b63db68933 /src/glsl/README
parentd8ab9aac54c3b6e4d97016172527d4b7c85b27a2 (diff)
glsl: Update README talking about multi-instruction operations.
The previous thing taking multiple instructions ended up being handled at the IR level, as we suggested would be the common result. Pick a new one.
Diffstat (limited to 'src/glsl/README')
-rw-r--r--src/glsl/README8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/glsl/README b/src/glsl/README
index 2e501d6206..7e97b48059 100644
--- a/src/glsl/README
+++ b/src/glsl/README
@@ -156,10 +156,10 @@ for the 965 fragment shader backend when that is developed.
Q: How should I expand instructions that take multiple backend instructions?
Sometimes you'll have to do the expansion in your code generation --
-see, for example, ir_to_mesa.cpp's handling of ir_binop_mul for
-matrices. However, in many cases you'll want to do a pass over the IR
-to convert non-native instructions to a series of native instructions.
-For example, for the Mesa backend we have ir_div_to_mul_rcp.cpp because
+see, for example, ir_to_mesa.cpp's handling of ir_unop_sqrt. However,
+in many cases you'll want to do a pass over the IR to convert
+non-native instructions to a series of native instructions. For
+example, for the Mesa backend we have ir_div_to_mul_rcp.cpp because
Mesa IR (and many hardware backends) only have a reciprocal
instruction, not a divide. Implementing non-native instructions this
way gives the chance for constant folding to occur, so (a / 2.0)