diff options
author | Eric Anholt <eric@anholt.net> | 2011-01-17 18:34:43 -0800 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2011-01-18 10:17:34 -0800 |
commit | 754b9c5363aa7ae5f47c88c78790b3fe35c07403 (patch) | |
tree | f6a82ee02a2f2f7c9a130c394bd35b425ecd5e86 /src/glsl/builtins | |
parent | 5b58b8c579f06edc2e5ead011e2544eadfbfb77a (diff) |
ra: Trade off some space to get time efficiency in ra_set_finalize().
Our use of the register allocator in i965 is somewhat unusual.
Whereas most architectures would have a smaller set of registers with
fewer register classes and reuse that across compilation, we have 1,
2, and 4-register classes (usually) and a variable number up to 128
registers per compile depending on how many setup parameters and push
constants are present. As a result, when compiling large numbers of
programs (as with glean texCombine going through ff_fragment_shader),
we spent much of our CPU time in computing the q[] array. By keeping
a separate list of what the conflicts are for a particular reg, we
reduce glean texCombine time 17.0% +/- 2.3% (n=5).
We don't expect this optimization to be useful for 915, which will
have a constant register set, but it would be useful if we were switch
to this register allocator for Mesa IR.
Diffstat (limited to 'src/glsl/builtins')
0 files changed, 0 insertions, 0 deletions