[intel] Add more cliprect modes to cover other meanings for batch emits.

The previous change gave us only two modes, one which looped over the batch
per cliprect (3d drawing) and one that didn't (state updeast).
However, we really want 4:

- Batch doesn't care about cliprects (state updates)
- Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing)
- Batch needs to be executed just once (region fills, copies, etc.)
- Batch already includes cliprect handling, and must be flushed by unlock time
  (copybuffers, clears).

All callers should now be fixed to use one of these states for any batchbuffer
emits.  Thanks to Keith Whitwell for pointing out the failure.

5 files changed, 26 insertions, 28 deletions

diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 412d146fe1..be4fdff7d6 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -295,7 +295,7 @@ i830_emit_invarient_state(struct intel_context *intel)
 {
    BATCH_LOCALS;
 
-   BEGIN_BATCH(40, 0);
+   BEGIN_BATCH(40, IGNORE_CLIPRECTS);
 
    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
    OUT_BATCH(0);
@@ -372,15 +372,7 @@ i830_emit_invarient_state(struct intel_context *intel)
 
 
 #define emit( intel, state, size )			\
-do {							\
-   int k;						\
-   BEGIN_BATCH(size / sizeof(GLuint), 0);		\
-   for (k = 0 ; k < size / sizeof(GLuint) ; k++) {	\
-      if (0) _mesa_printf("  0x%08x\n", state[k]);		\
-      OUT_BATCH(state[k]);				\
-   }							\
-   ADVANCE_BATCH();					\
-} while (0)
+   intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
 
 static GLuint
 get_dirty(struct i830_hw_state *state)
@@ -473,13 +465,13 @@ i830_do_emit_state(struct intel_context *intel)
 
    if (dirty & I830_UPLOAD_CTX) {
       DBG("I830_UPLOAD_CTX:\n");
-      emit(i830, state->Ctx, sizeof(state->Ctx));
+      emit(intel, state->Ctx, sizeof(state->Ctx));
 
    }
 
    if (dirty & I830_UPLOAD_BUFFERS) {
       DBG("I830_UPLOAD_BUFFERS:\n");
-      BEGIN_BATCH(I830_DEST_SETUP_SIZE + 2, 0);
+      BEGIN_BATCH(I830_DEST_SETUP_SIZE + 2, IGNORE_CLIPRECTS);
       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
       OUT_RELOC(state->draw_region->buffer,
@@ -505,14 +497,14 @@ i830_do_emit_state(struct intel_context *intel)
    
    if (dirty & I830_UPLOAD_STIPPLE) {
       DBG("I830_UPLOAD_STIPPLE:\n");
-      emit(i830, state->Stipple, sizeof(state->Stipple));
+      emit(intel, state->Stipple, sizeof(state->Stipple));
    }
 
    for (i = 0; i < I830_TEX_UNITS; i++) {
       if ((dirty & I830_UPLOAD_TEX(i))) {
          DBG("I830_UPLOAD_TEX(%d):\n", i);
 
-         BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, 0);
+         BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, IGNORE_CLIPRECTS);
          OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
 
          if (state->tex_buffer[i]) {
@@ -539,7 +531,7 @@ i830_do_emit_state(struct intel_context *intel)
       if (dirty & I830_UPLOAD_TEXBLEND(i)) {
          DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i,
              state->TexBlendWordsUsed[i]);
-         emit(i830, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4);
+         emit(intel, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4);
       }
    }
 
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 8b45cdacbb..8e5dd453ab 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -170,7 +170,7 @@ i915_emit_invarient_state(struct intel_context *intel)
 {
    BATCH_LOCALS;
 
-   BEGIN_BATCH(200, 0);
+   BEGIN_BATCH(200, IGNORE_CLIPRECTS);
 
    OUT_BATCH(_3DSTATE_AA_CMD |
              AA_LINE_ECAAR_WIDTH_ENABLE |
@@ -229,7 +229,7 @@ i915_emit_invarient_state(struct intel_context *intel)
 
 
 #define emit(intel, state, size )		     \
-   intel_batchbuffer_data(intel->batch, state, size, 0 )
+   intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
 
 static GLuint
 get_dirty(struct i915_hw_state *state)
@@ -354,7 +354,7 @@ i915_do_emit_state(struct intel_context *intel)
    if (dirty & I915_UPLOAD_BUFFERS) {
       if (INTEL_DEBUG & DEBUG_STATE)
          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
-      BEGIN_BATCH(I915_DEST_SETUP_SIZE + 2, 0);
+      BEGIN_BATCH(I915_DEST_SETUP_SIZE + 2, IGNORE_CLIPRECTS);
       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
       OUT_RELOC(state->draw_region->buffer,
@@ -400,7 +400,7 @@ i915_do_emit_state(struct intel_context *intel)
          if (dirty & I915_UPLOAD_TEX(i))
             nr++;
 
-      BEGIN_BATCH(2 + nr * 3, 0);
+      BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
       for (i = 0; i < I915_TEX_UNITS; i++)
@@ -424,7 +424,7 @@ i915_do_emit_state(struct intel_context *intel)
          }
       ADVANCE_BATCH();
 
-      BEGIN_BATCH(2 + nr * 3, 0);
+      BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
       for (i = 0; i < I915_TEX_UNITS; i++)
diff --git a/src/mesa/drivers/dri/i915/intel_context.c b/src/mesa/drivers/dri/i915/intel_context.c
index ce77b57a3e..32655b87d8 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -832,5 +832,11 @@ void UNLOCK_HARDWARE( struct intel_context *intel )
 
    if (INTEL_DEBUG & DEBUG_LOCK)
       _mesa_printf("%s - unlocked\n", __progname);
-} 
+
+   /**
+    * Nothing should be left in batch outside of LOCK/UNLOCK which references
+    * cliprects.
+    */
+   assert(intel->batch->cliprect_mode != REFERENCES_CLIPRECTS);
+}
 
diff --git a/src/mesa/drivers/dri/i915/intel_render.c b/src/mesa/drivers/dri/i915/intel_render.c
index 473ddb8393..bcf50324b1 100644
--- a/src/mesa/drivers/dri/i915/intel_render.c
+++ b/src/mesa/drivers/dri/i915/intel_render.c
@@ -113,7 +113,7 @@ intelDmaPrimitive(struct intel_context *intel, GLenum prim)
       fprintf(stderr, "%s %s\n", __FUNCTION__, _mesa_lookup_enum_by_nr(prim));
    INTEL_FIREVERTICES(intel);
    intel->vtbl.reduced_primitive_state(intel, reduced_prim[prim]);
-   intelStartInlinePrimitive(intel, hw_prim[prim], INTEL_BATCH_CLIPRECTS);
+   intelStartInlinePrimitive(intel, hw_prim[prim], LOOP_CLIPRECTS);
 }
 
 
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c
index 8d27e3cf03..6ed54b072a 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -103,7 +103,7 @@ intelStartInlinePrimitive(struct intel_context *intel,
 
 /*    _mesa_printf("%s *", __progname); */
 
-   intel_wait_flips(intel, batch_flags);
+   intel_wait_flips(intel);
 
    /* Emit a slot which will be filled with the inline primitive
     * command later.
@@ -129,11 +129,11 @@ void
 intelWrapInlinePrimitive(struct intel_context *intel)
 {
    GLuint prim = intel->prim.primitive;
-   GLuint cliprects_enable = intel->batch->cliprects_enable;
+   enum cliprect_mode cliprect_mode = intel->batch->cliprect_mode;
 
    intel_flush_inline_primitive(intel);
    intel_batchbuffer_flush(intel->batch);
-   intelStartInlinePrimitive(intel, prim, cliprects_enable);  /* ??? */
+   intelStartInlinePrimitive(intel, prim, cliprect_mode);  /* ??? */
 }
 
 GLuint *
@@ -942,7 +942,7 @@ intelRasterPrimitive(GLcontext * ctx, GLenum rprim, GLuint hwprim)
    if (hwprim != intel->prim.primitive) {
       INTEL_FIREVERTICES(intel);
 
-      intelStartInlinePrimitive(intel, hwprim, INTEL_BATCH_CLIPRECTS);
+      intelStartInlinePrimitive(intel, hwprim, LOOP_CLIPRECTS);
    }
 }
 
@@ -1079,10 +1079,10 @@ intel_meta_draw_poly(struct intel_context *intel,
    if (!was_locked)
        LOCK_HARDWARE(intel);
 
-   /* All 3d primitives should be emitted with INTEL_BATCH_CLIPRECTS,
+   /* All 3d primitives should be emitted with LOOP_CLIPRECTS,
     * otherwise the drawing origin (DR4) might not be set correctly.
     */
-   intelStartInlinePrimitive(intel, PRIM3D_TRIFAN, INTEL_BATCH_CLIPRECTS);
+   intelStartInlinePrimitive(intel, PRIM3D_TRIFAN, LOOP_CLIPRECTS);
    vb = (union fi *) intelExtendInlinePrimitive(intel, n * 6);
 
    for (i = 0; i < n; i++) {