diff options
| author | Nian Wu <nian.wu@intel.com> | 2007-03-19 17:00:19 +0800 |
|---|---|---|
| committer | Nian Wu <nian.wu@intel.com> | 2007-03-19 17:00:19 +0800 |
| commit | e01ee3da577f177e77153f3a33d39e13f5e3f9cb (patch) | |
| tree | 14bcfd5a30a5b24b22a9b773b4ba6211e50e8958 /src/mesa/drivers/dri/i915 | |
| parent | fd1b1fce3faaf40af201a5b06a84df62c855fb12 (diff) | |
| parent | 77544d7b7d7c6fd03c0df81dca07f1bb3a67c119 (diff) | |
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
Diffstat (limited to 'src/mesa/drivers/dri/i915')
| -rw-r--r-- | src/mesa/drivers/dri/i915/i915_reg.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/i915_state.c | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/i915_vtbl.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h index 3ba792a234..694cd4c8c3 100644 --- a/src/mesa/drivers/dri/i915/i915_reg.h +++ b/src/mesa/drivers/dri/i915/i915_reg.h @@ -138,7 +138,7 @@ /* 3DSTATE_DEPTH_SUBRECT_DISABLE, p160 */ -#define _3DSTATE_DEPTH_SUBRECT_DISABLE (CMD_3D | (0x1c<<24) | (0x11<19) | 0x2) +#define _3DSTATE_DEPTH_SUBRECT_DISABLE (CMD_3D | (0x1c<<24) | (0x11<<19) | 0x2) /* p161 */ #define _3DSTATE_DST_BUF_VARS_CMD (CMD_3D | (0x1d<<24) | (0x85<<16)) diff --git a/src/mesa/drivers/dri/i915/i915_state.c b/src/mesa/drivers/dri/i915/i915_state.c index fd11e10652..5e00e6597b 100644 --- a/src/mesa/drivers/dri/i915/i915_state.c +++ b/src/mesa/drivers/dri/i915/i915_state.c @@ -813,7 +813,7 @@ static void i915_init_packets( i915ContextPtr i915 ) I1_LOAD_S(4) | I1_LOAD_S(5) | I1_LOAD_S(6) | - (4)); + (3)); i915->state.Ctx[I915_CTXREG_LIS2] = 0; i915->state.Ctx[I915_CTXREG_LIS4] = 0; i915->state.Ctx[I915_CTXREG_LIS5] = 0; diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 2936a0fb72..b533e153be 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -180,7 +180,7 @@ static void i915_emit_invarient_state( intelContextPtr intel ) */ OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | - (1)); + (0)); OUT_BATCH(0); /* XXX: Use this */ |