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authorEric Anholt <eric@anholt.net>2007-10-04 12:07:25 -0700
committerEric Anholt <eric@anholt.net>2007-10-04 12:28:49 -0700
commit77e0523fb7769df4bf43747e136b1653b2421b97 (patch)
tree27337de5a5460aad8428969a504621c98e95fb16 /src/mesa/drivers/dri/i965/brw_clip_state.c
parent0fc9efd8f0b1b6c4e3525a50e3478e5aef72531a (diff)
[965] Replace various alignment code with a shared ALIGN() macro.
In the process, fix some alignment issues: - Scratch space allocation was aligned into units of 1KB, while the allocation wanted units of bytes, so we never allocated enough space for scratch. - GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_clip_state.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_clip_state.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index ae46d7a86e..ba2f0edf51 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -43,7 +43,8 @@ static void upload_clip_unit( struct brw_context *brw )
memset(&clip, 0, sizeof(clip));
/* CACHE_NEW_CLIP_PROG */
- clip.thread0.grf_reg_count = ((brw->clip.prog_data->total_grf-1) & ~15) / 16;
+ clip.thread0.grf_reg_count =
+ ALIGN(brw->clip.prog_data->total_grf, 16) / 16 - 1;
clip.thread0.kernel_start_pointer = brw->clip.prog_gs_offset >> 6;
clip.thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length;
clip.thread3.const_urb_entry_read_length = brw->clip.prog_data->curb_read_length;