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authorEric Anholt <eric@anholt.net>2010-01-29 11:18:26 -0800
committerEric Anholt <eric@anholt.net>2010-02-25 10:53:06 -0800
commit7ee590424c974cb10882e9c4664a6024595fc9de (patch)
tree01b172bf9f3ed059fbe0d24a8685b2838f9a7890 /src/mesa/drivers/dri/i965/brw_context.h
parent9dce60f35b25f4f5605b22d75447bac5d9f55515 (diff)
i965: Start adding support for the Sandybridge CC unit.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_context.h')
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h15
1 files changed, 14 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 21c4cd38a7..ea89d4f6fa 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -282,6 +282,9 @@ struct brw_vs_ouput_sizes {
enum brw_cache_id {
+ BRW_BLEND_STATE,
+ BRW_DEPTH_STENCIL_STATE,
+ BRW_COLOR_CALC_STATE,
BRW_CC_VP,
BRW_CC_UNIT,
BRW_WM_PROG,
@@ -354,6 +357,9 @@ struct brw_tracked_state {
/* Flags for brw->state.cache.
*/
+#define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
+#define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
+#define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
#define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
#define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
#define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
@@ -643,9 +649,16 @@ struct brw_context
struct {
+ /* gen4 */
dri_bo *prog_bo;
- dri_bo *state_bo;
dri_bo *vp_bo;
+
+ /* gen6 */
+ dri_bo *blend_state_bo;
+ dri_bo *depth_stencil_state_bo;
+ dri_bo *color_calc_state_bo;
+
+ dri_bo *state_bo;
} cc;
struct {