diff options
| author | Eric Anholt <eric@anholt.net> | 2010-12-03 11:49:29 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-12-06 00:14:23 -0800 |
| commit | 245662f3083795e272fe9ef5d4cbeb6d048cf0e5 (patch) | |
| tree | 494fafc8c656d1f8c36612fa353a536cbdbc889e /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | 3f8bcb0d998820594ea288e4607462fa4479859f (diff) | |
i965: Add support for the instruction compression bits on gen6.
Since the 8-wide first-quarter and 16-wide first-half have the same
bit encoding, we now need to track "do you want instruction
compression" in the compile state.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 239586a036..5c5b8259e1 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -462,6 +462,13 @@ #define BRW_COMPRESSION_2NDHALF 1 #define BRW_COMPRESSION_COMPRESSED 2 +#define GEN6_COMPRESSION_1Q 0 +#define GEN6_COMPRESSION_2Q 1 +#define GEN6_COMPRESSION_3Q 2 +#define GEN6_COMPRESSION_4Q 3 +#define GEN6_COMPRESSION_1H 0 +#define GEN6_COMPRESSION_2H 2 + #define BRW_CONDITIONAL_NONE 0 #define BRW_CONDITIONAL_Z 1 #define BRW_CONDITIONAL_NZ 2 |