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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-29 13:59:03 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-29 14:02:37 +0800 |
| commit | 0a1910c26760762eb8d67f68dfd87494ab479e38 (patch) | |
| tree | 856b04c9a7db710693e53dbf27ec3ee3d4fd9963 /src/mesa/drivers/dri/i965/brw_draw.c | |
| parent | 28b57c56e21943055f8d3c08822c4f632468b0b1 (diff) | |
i965: Always set tiling for depth buffer on sandybridge
Sandybridge only support tiling depth buffer, always set tiling bit.
Fix 'fbo_firecube' demo.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_draw.c')
0 files changed, 0 insertions, 0 deletions