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authorEric Anholt <eric@anholt.net>2010-12-03 11:49:29 -0800
committerEric Anholt <eric@anholt.net>2010-12-06 00:14:23 -0800
commit245662f3083795e272fe9ef5d4cbeb6d048cf0e5 (patch)
tree494fafc8c656d1f8c36612fa353a536cbdbc889e /src/mesa/drivers/dri/i965/brw_eu.h
parent3f8bcb0d998820594ea288e4607462fa4479859f (diff)
i965: Add support for the instruction compression bits on gen6.
Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_eu.h')
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index a4904b7098..4dbdc52210 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -33,6 +33,7 @@
#ifndef BRW_EU_H
#define BRW_EU_H
+#include <stdbool.h>
#include "brw_structs.h"
#include "brw_defines.h"
#include "program/prog_instruction.h"
@@ -106,10 +107,12 @@ struct brw_compile {
/* Allow clients to push/pop instruction state:
*/
struct brw_instruction stack[BRW_EU_MAX_INSN_STACK];
+ bool compressed_stack[BRW_EU_MAX_INSN_STACK];
struct brw_instruction *current;
GLuint flag_value;
GLboolean single_program_flow;
+ bool compressed;
struct brw_context *brw;
struct brw_glsl_label *first_label; /**< linked list of labels */