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authorZou Nan hai <nanhai.zou@intel.com>2007-09-29 15:00:52 +0800
committerZou Nan hai <nanhai.zou@intel.com>2007-09-29 15:00:52 +0800
commitb0b48798c7e854d2e36e0317bf94b7385e815242 (patch)
treeecf0523f50fb3bf1458bc832046eb222068c5774 /src/mesa/drivers/dri/i965/brw_eu_emit.c
parente75ae0dc792b9fe599b68d7a9ea0ab22413da424 (diff)
support continue, fix conditional
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_eu_emit.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 7b95fbdac0..95f9f02753 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -611,6 +611,20 @@ struct brw_instruction *brw_BREAK(struct brw_compile *p)
return insn;
}
+struct brw_instruction *brw_CONT(struct brw_compile *p)
+{
+ struct brw_instruction *insn;
+ insn = next_insn(p, BRW_OPCODE_CONTINUE);
+ brw_set_dest(insn, brw_ip_reg());
+ brw_set_src0(insn, brw_ip_reg());
+ brw_set_src1(insn, brw_imm_d(0x0));
+ insn->header.compression_control = BRW_COMPRESSION_NONE;
+ insn->header.execution_size = BRW_EXECUTE_8;
+ insn->header.mask_control = BRW_MASK_DISABLE;
+ insn->bits3.if_else.pad0 = 0;
+ return insn;
+}
+
/* DO/WHILE loop:
*/
struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)