diff options
| author | Eric Anholt <eric@anholt.net> | 2010-12-09 09:36:17 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-12-09 20:25:34 -0800 |
| commit | 15566183a64ef3f9940962a3b08b1c3469c98566 (patch) | |
| tree | d5e5a457bf2e6645f4c741121de63ffc35c6d2e4 /src/mesa/drivers/dri/i965/brw_eu_emit.c | |
| parent | 83bdd402aa3b83c121d6764328f831b1629e41a2 (diff) | |
i965: Add support for gen6 constant-index constant loading.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_eu_emit.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index b20d88280f..93ccdde44b 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1708,9 +1708,13 @@ void brw_dp_READ_4_vs(struct brw_compile *p, GLuint location, GLuint bind_table_index) { + struct intel_context *intel = &p->brw->intel; struct brw_instruction *insn; GLuint msg_reg_nr = 1; + if (intel->gen >= 6) + location /= 16; + /* Setup MRF[1] with location/offset into const buffer */ brw_push_insn_state(p); brw_set_compression_control(p, BRW_COMPRESSION_NONE); @@ -1729,7 +1733,11 @@ void brw_dp_READ_4_vs(struct brw_compile *p, insn->header.mask_control = BRW_MASK_DISABLE; brw_set_dest(p, insn, dest); - brw_set_src0(insn, brw_null_reg()); + if (intel->gen >= 6) { + brw_set_src0(insn, brw_message_reg(msg_reg_nr)); + } else { + brw_set_src0(insn, brw_null_reg()); + } brw_set_dp_read_message(p->brw, insn, |