diff options
author | Eric Anholt <eric@anholt.net> | 2010-12-01 14:02:14 -0800 |
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committer | Eric Anholt <eric@anholt.net> | 2010-12-01 16:14:34 -0800 |
commit | 843a6a308e05bd4bf2056e08ec65ac4770097b93 (patch) | |
tree | 9bc85f5a8651a59dd709bf8404cc9d55ee408e8f /src/mesa/drivers/dri/i965/brw_eu_emit.c | |
parent | 00e5a743e2ee3981a34b95067a97fa73c0f5d779 (diff) |
i965: Add support for gen6 CONTINUE instruction emit.
At this point, piglit tests for fragment shader loops are working.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_eu_emit.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 7eb7bdfa1e..945f50d110 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1050,6 +1050,26 @@ struct brw_instruction *brw_BREAK(struct brw_compile *p, int pop_count) return insn; } +struct brw_instruction *brw_CONT_gen6(struct brw_compile *p, + struct brw_instruction *do_insn) +{ + struct brw_instruction *insn; + int br = 2; + + insn = next_insn(p, BRW_OPCODE_CONTINUE); + brw_set_dest(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + brw_set_src0(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + brw_set_dest(insn, brw_ip_reg()); + brw_set_src0(insn, brw_ip_reg()); + brw_set_src1(insn, brw_imm_d(0x0)); + + insn->bits3.break_cont.uip = br * (do_insn - insn); + + insn->header.compression_control = BRW_COMPRESSION_NONE; + insn->header.execution_size = BRW_EXECUTE_8; + return insn; +} + struct brw_instruction *brw_CONT(struct brw_compile *p, int pop_count) { struct brw_instruction *insn; @@ -2087,7 +2107,9 @@ brw_set_uip_jip(struct brw_compile *p) /* JIP is set at CONTINUE emit time, since that's when we * know where the start of the loop is. */ - insn->bits3.break_cont.uip = br * (brw_find_next_block_end(p, ip) - ip); + insn->bits3.break_cont.jip = br * (brw_find_next_block_end(p, ip) - ip); + assert(insn->bits3.break_cont.uip != 0); + assert(insn->bits3.break_cont.jip != 0); break; } } |