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authorEric Anholt <eric@anholt.net>2011-01-10 15:45:28 -0800
committerEric Anholt <eric@anholt.net>2011-01-10 17:21:54 -0800
commitc0cdae03685056e170c25da7d46aed959176d652 (patch)
treeda0fd3d59d757a7c605a38289e5567af13ef2a48 /src/mesa/drivers/dri/i965/brw_fallback.c
parent6bdc31942138f4dff5a701f26fe186a6e2e92275 (diff)
i965: Use a new miptree to avoid software fallbacks due to drawing offset.
When attaching a small mipmap level to an FBO, the original gen4 didn't have the bits to support rendering to it. Instead of falling back, just blit it to a new little miptree just for it, and let it get revalidated into the stack later just like any other new teximage. Bug #30365.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fallback.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fallback.c29
1 files changed, 1 insertions, 28 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c
index 7262cf6958..82356a5bc0 100644
--- a/src/mesa/drivers/dri/i965/brw_fallback.c
+++ b/src/mesa/drivers/dri/i965/brw_fallback.c
@@ -80,33 +80,6 @@ static GLboolean do_check_fallback(struct brw_context *brw)
return GL_TRUE;
}
- /* _NEW_BUFFERS */
- if (!brw->has_surface_tile_offset) {
- for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
- struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
- struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-
- /* The original gen4 hardware couldn't set up WM surfaces pointing
- * at an offset within a tile, which can happen when rendering to
- * anything but the base level of a texture or the +X face/0 depth.
- * This was fixed with the 4 Series hardware.
- *
- * For these original chips, you would have to make the depth and
- * color destination surfaces include information on the texture
- * type, LOD, face, and various limits to use them as a destination.
- * I would have done this, but there's also a nasty requirement that
- * the depth and the color surfaces all be of the same LOD, which
- * may be a worse requirement than this alignment. (Also, we may
- * want to just demote the texture to untiled, instead).
- */
- if (irb->region && irb->region->tiling != I915_TILING_NONE &&
- (irb->region->draw_offset & 4095)) {
- DBG("FALLBACK: non-tile-aligned destination for tiled FBO\n");
- return GL_TRUE;
- }
- }
- }
-
return GL_FALSE;
}
@@ -117,7 +90,7 @@ static void check_fallback(struct brw_context *brw)
const struct brw_tracked_state brw_check_fallback = {
.dirty = {
- .mesa = _NEW_BUFFERS | _NEW_RENDERMODE | _NEW_TEXTURE | _NEW_STENCIL,
+ .mesa = _NEW_RENDERMODE | _NEW_TEXTURE | _NEW_STENCIL,
.brw = 0,
.cache = 0
},