diff options
| author | Ian Romanick <ian.d.romanick@intel.com> | 2010-11-18 11:05:32 -0800 |
|---|---|---|
| committer | Ian Romanick <ian.d.romanick@intel.com> | 2010-11-19 15:00:25 -0800 |
| commit | f2616e56de8a48360cae8f269727b58490555f4d (patch) | |
| tree | 56462288844e777618344e9f7830b5c3eb1f1f02 /src/mesa/drivers/dri/i965/brw_fs.cpp | |
| parent | 04ffbe1ac6a82ac5cce843afa15ffdfa4ef78103 (diff) | |
glsl: Add ir_unop_sin_reduced and ir_unop_cos_reduced
The operate just like ir_unop_sin and ir_unop_cos except that they
expect their inputs to be limited to the range [-pi, pi]. Several
GPUs require this limited range for their sine and cosine
instructions, so having these as operations (along with a to-be-written
lowering pass) helps this architectures.
These new operations also matche the semantics of the
GL_ARB_fragment_program SCS instruction. Having these as operations
helps in generating GLSL IR directly from assembly fragment programs.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index ac795e0bda..164f89eace 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -778,9 +778,11 @@ fs_visitor::visit(ir_expression *ir) assert(!"not reached: should be handled by ir_explog_to_explog2"); break; case ir_unop_sin: + case ir_unop_sin_reduced: emit_math(FS_OPCODE_SIN, this->result, op[0]); break; case ir_unop_cos: + case ir_unop_cos_reduced: emit_math(FS_OPCODE_COS, this->result, op[0]); break; |