diff options
author | Xiang, Haihao <haihao.xiang@intel.com> | 2009-07-13 10:48:43 +0800 |
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committer | Xiang, Haihao <haihao.xiang@intel.com> | 2009-07-13 11:01:13 +0800 |
commit | 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 (patch) | |
tree | 61effe693f29512148ce333209f7e1ee01e5f729 /src/mesa/drivers/dri/i965/brw_gs.c | |
parent | f030e2ba17a3b859d30017cfd990552d3af4bad3 (diff) |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_gs.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index a8b74a0afe..48c2b9a41c 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -54,12 +54,17 @@ static void compile_gs_prog( struct brw_context *brw, memset(&c, 0, sizeof(c)); c.key = *key; - + c.need_ff_sync = BRW_IS_IGDNG(brw); /* Need to locate the two positions present in vertex + header. * These are currently hardcoded: */ c.nr_attrs = brw_count_bits(c.key.attrs); - c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */ + + if (BRW_IS_IGDNG(brw)) + c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */ + else + c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */ + c.nr_bytes = c.nr_regs * REG_SIZE; |