diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2007-01-17 10:39:50 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2007-01-17 10:39:50 +0800 |
| commit | 747c9129c0b592941b14c290ff3d8ab22ad66acb (patch) | |
| tree | bbf80c50c3ddf49e3c345956556aeccc341412cc /src/mesa/drivers/dri/i965/brw_gs.h | |
| parent | afba8f0d30974bf7fbb9533f23eb2f92d49ac526 (diff) | |
I965: fix bug#9625-get the correct PV for quardstrip
The order of vertices in payload for quardstrip is (0, 1, 3, 2),
so the PV for quardstrip is c->reg.vertex[2].
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_gs.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_gs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h index f9aa71d919..29a4e80ce1 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.h +++ b/src/mesa/drivers/dri/i965/brw_gs.h @@ -67,6 +67,7 @@ struct brw_gs_compile { #define ATTR_SIZE (4*4) void brw_gs_quads( struct brw_gs_compile *c ); +void brw_gs_quad_strip( struct brw_gs_compile *c ); void brw_gs_tris( struct brw_gs_compile *c ); void brw_gs_lines( struct brw_gs_compile *c ); void brw_gs_points( struct brw_gs_compile *c ); |