diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-29 15:18:37 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-29 15:18:37 +0800 |
| commit | d4da253b298677c63def5f2f774608d660be31a1 (patch) | |
| tree | 776816d78c567a2dbfaa56fc90872c092454bb5b /src/mesa/drivers/dri/i965/brw_misc_state.c | |
| parent | b27a809266bd664cd101fcfdf20886cc2b7df787 (diff) | |
Revert "i965: Always set tiling for depth buffer on sandybridge"
This reverts commit 0a1910c26760762eb8d67f68dfd87494ab479e38.
oops, shouldn't apply tiling depth buffer for other chips as well.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 7a334126f2..6eeaba7772 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -289,7 +289,7 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(((region->pitch * region->cpp) - 1) | (format << 18) | (BRW_TILEWALK_YMAJOR << 26) | - (1 << 27) | + ((region->tiling != I915_TILING_NONE) << 27) | (BRW_SURFACE_2D << 29)); OUT_RELOC(region->buffer, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, |