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authorZhenyu Wang <zhenyuw@linux.intel.com>2010-06-29 10:49:55 +0800
committerEric Anholt <eric@anholt.net>2010-07-08 12:50:53 -0700
commit04466795511bc93e4301e71b9e0c7a9154ecf042 (patch)
tree30e3515ada62af350fd162eddded17fdbf5415ec /src/mesa/drivers/dri/i965/brw_structs.h
parent9cc6b5b043044bc0b74502f3cca03a8423ed25b2 (diff)
i965: Add definitions for Sandybridge DP write/read messages.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_structs.h')
-rw-r--r--src/mesa/drivers/dri/i965/brw_structs.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 2a7fa5b699..205d1b90fd 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1657,6 +1657,34 @@ struct brw_instruction
GLuint end_of_thread:1;
} dp_write_gen5;
+ /* Sandybridge DP for sample cache, constant cache, render cache */
+ struct {
+ GLuint binding_table_index:8;
+ GLuint msg_control:5;
+ GLuint msg_type:3;
+ GLuint pad0:3;
+ GLuint header_present:1;
+ GLuint response_length:5;
+ GLuint msg_length:4;
+ GLuint pad1:2;
+ GLuint end_of_thread:1;
+ } dp_sampler_const_cache;
+
+ struct {
+ GLuint binding_table_index:8;
+ GLuint msg_control:3;
+ GLuint slot_group_select:1;
+ GLuint pixel_scoreboard_clear:1;
+ GLuint msg_type:4;
+ GLuint send_commit_msg:1;
+ GLuint pad0:1;
+ GLuint header_present:1;
+ GLuint response_length:5;
+ GLuint msg_length:4;
+ GLuint pad1:2;
+ GLuint end_of_thread:1;
+ } dp_render_cache;
+
struct {
GLuint pad:16;
GLuint response_length:4;