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authorEric Anholt <eric@anholt.net>2009-06-05 23:16:44 +0000
committerEric Anholt <eric@anholt.net>2009-06-17 21:01:48 -0700
commit0f328c90dbc893e15005f2ab441d309c1c176245 (patch)
tree80a82e10b357e4cd595d0e3ef744ebce108e43ec /src/mesa/drivers/dri/i965/brw_structs.h
parent46000cecc32104702fcb0de5a842d11b18c41c6b (diff)
i965: Fall back or appropriately adjust offsets of drawing to tiled regions.
3D rendering to tiled textures was being done with non-tile-aligned offsets. The G4X hardware has fields to let us support it easily and correctly, while the pre-G4X hardware requires a path full of suffering, so we just fall back.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_structs.h')
-rw-r--r--src/mesa/drivers/dri/i965/brw_structs.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 89e2981203..040ec9327d 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1075,7 +1075,7 @@ struct brw_surface_state
GLuint y_offset:4;
GLuint pad0:1;
GLuint x_offset:7;
- } ss5; /* NEW in Integrated Graphics Device */
+ } ss5; /* New in G4X */
};