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authorZhenyu Wang <zhenyuw@linux.intel.com>2010-08-31 09:54:44 +0800
committerZhenyu Wang <zhenyuw@linux.intel.com>2010-08-31 09:58:18 +0800
commit24ff42e7d56ac489caeca6b5ffcc3091cc8194b5 (patch)
tree67bdde14f87fb7aa7e2692ef219d184f456aac9e /src/mesa/drivers/dri/i965/brw_structs.h
parentbe7816f2b7f0b064a47fb3f101477ad5dba74017 (diff)
i965: fix depth test on sandybridge
This includes several corrections for fixing depth test on sandybridge. Fix wrong bits definition in depth stencil state. Fix wrong order of state buffer offset in 3DSTATE_CC_STATE_POINTERS command. Correctly use buffer width parameter in depth buffer setting. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_structs.h')
-rw-r--r--src/mesa/drivers/dri/i965/brw_structs.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index cdd2998627..2a118e01c5 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -750,7 +750,7 @@ struct gen6_depth_stencil_state
} ds1;
struct {
- GLuint pad0:25;
+ GLuint pad0:26;
GLuint depth_write_enable:1;
GLuint depth_test_func:3;
GLuint pad1:1;