i965: Set render_cache_read_write surface state bit on gen6 constant surfs.

This is said to be required in the spec, even when you aren't doing writes.

1 files changed, 5 insertions, 0 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 0e1f3c9bb8..d341187c1b 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1179,6 +1179,11 @@ struct brw_surface_state
       GLuint cube_pos_x:1; 
       GLuint cube_neg_x:1; 
       GLuint pad:4;
+      /* Required on gen6 for surfaces accessed through render cache messages.
+       */
+      GLuint render_cache_read_write:1;
+      /* Ironlake and newer: instead of replicating one of the texels */
+      GLuint cube_corner_average:1;
       GLuint mipmap_layout_mode:1; 
       GLuint vert_line_stride_ofs:1; 
       GLuint vert_line_stride:1;