diff options
| author | Eric Anholt <eric@anholt.net> | 2009-06-03 16:40:20 +0000 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-06-04 14:00:43 +0000 |
| commit | 1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e (patch) | |
| tree | 2cd5c5303ec85edfc47ab8f80e60a88134f461e0 /src/mesa/drivers/dri/i965/brw_tex_layout.c | |
| parent | 165ae5e2fb57bdb64b4cf01271b4effeb811f675 (diff) | |
intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_tex_layout.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_tex_layout.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index be8ce546a9..5c5455813a 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -40,7 +40,8 @@ #define FILE_DEBUG_FLAG DEBUG_MIPTREE GLboolean brw_miptree_layout(struct intel_context *intel, - struct intel_mipmap_tree *mt) + struct intel_mipmap_tree *mt, + uint32_t tiling) { /* XXX: these vary depending on image format: */ /* GLint align_w = 4; */ @@ -64,8 +65,8 @@ GLboolean brw_miptree_layout(struct intel_context *intel, mt->pitch = ALIGN(width, align_w); pack_y_pitch = (height + 3) / 4; } else { - mt->pitch = intel_miptree_pitch_align (intel, mt, mt->width0); - pack_y_pitch = ALIGN(mt->height0, align_h); + mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0); + pack_y_pitch = ALIGN(mt->height0, align_h); } pack_x_pitch = mt->pitch; @@ -122,7 +123,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel, } default: - i945_miptree_layout_2d(intel, mt); + i945_miptree_layout_2d(intel, mt, tiling); break; } DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__, |