diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-04-19 15:51:50 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-04-21 10:11:02 +0800 |
| commit | cdcef6cbf4dd80047819e9098e34a3b98bd502a4 (patch) | |
| tree | 712387517536e90d712c9851fc467ccbcf55a8ca /src/mesa/drivers/dri/i965/brw_tex_layout.c | |
| parent | 9e258fc2bd6f2b9950606a0a92bb92c8959d9efd (diff) | |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_tex_layout.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_tex_layout.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index b1f56a8e64..9a215ab8a4 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -48,7 +48,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel, switch (mt->target) { case GL_TEXTURE_CUBE_MAP: - if (intel->is_ironlake) { + if (intel->gen == 5) { GLuint align_h = 2, align_w = 4; GLuint level; GLuint x = 0; |