diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2009-07-13 10:48:43 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2009-07-13 11:01:13 +0800 |
| commit | 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 (patch) | |
| tree | 61effe693f29512148ce333209f7e1ee01e5f729 /src/mesa/drivers/dri/i965/brw_urb.c | |
| parent | f030e2ba17a3b859d30017cfd990552d3af4bad3 (diff) | |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_urb.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_urb.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c index 47bc45c912..8c6f4355a6 100644 --- a/src/mesa/drivers/dri/i965/brw_urb.c +++ b/src/mesa/drivers/dri/i965/brw_urb.c @@ -146,7 +146,17 @@ static void recalculate_urb_fence( struct brw_context *brw ) brw->urb.constrained = 0; - if (BRW_IS_G4X(brw)) { + if (BRW_IS_IGDNG(brw)) { + brw->urb.nr_vs_entries = 128; + brw->urb.nr_sf_entries = 48; + if (check_urb_layout(brw)) { + goto done; + } else { + brw->urb.constrained = 1; + brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; + brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries; + } + } else if (BRW_IS_G4X(brw)) { brw->urb.nr_vs_entries = 64; if (check_urb_layout(brw)) { goto done; |