diff options
author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-08-20 14:37:19 -0700 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-08-20 16:17:39 -0700 |
commit | 93ba0055c325007656c14ba38302e21be3dc599f (patch) | |
tree | 31fba7f6e423a3cbeb315c31e54a47c86488817d /src/mesa/drivers/dri/i965/brw_vs_emit.c | |
parent | ffb5095d56c0f58a35e12d40bb4ffc869e4071bd (diff) |
i965: Add AccWrCtl support on Sandybridge.
Whenever the accumulator results are needed, this bit must be set.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vs_emit.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vs_emit.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 18eb845ed8..2f4653fbda 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1397,6 +1397,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) * of zeros followed by two sets of NDC coordinates: */ brw_set_access_mode(p, BRW_ALIGN_1); + brw_set_acc_write_control(p, 0); /* The VUE layout is documented in Volume 2a. */ if (intel->gen >= 6) { @@ -1578,6 +1579,8 @@ void brw_vs_emit(struct brw_vs_compile *c ) brw_set_access_mode(p, BRW_ALIGN_16); if_depth_in_loop[loop_depth] = 0; + brw_set_acc_write_control(p, 1); + for (insn = 0; insn < nr_insns; insn++) { GLuint i; struct prog_instruction *inst = &c->vp->program.Base.Instructions[insn]; |