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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-17 15:08:09 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-28 15:58:21 +0800 |
| commit | 18c3b754f974751550dc9505d50535365beac8f3 (patch) | |
| tree | 549c68473bf6716ecb4cd5cec80cbf687d4b97b9 /src/mesa/drivers/dri/i965/brw_wm_pass0.c | |
| parent | c8033f1b1ea118f3f47b7f3de557b7a8dcf11082 (diff) | |
i965: sandybridge pipe control workaround before write cache flush
Must issue a pipe control with any non-zero post sync op before
write cache flush = 1 pipe control.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_pass0.c')
0 files changed, 0 insertions, 0 deletions