diff options
author | Eric Anholt <eric@anholt.net> | 2010-11-11 09:30:16 -0800 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-12-06 00:14:22 -0800 |
commit | 16f8c823898fd71a3545457eacd2dc31ddeb3592 (patch) | |
tree | d99a9f727839f5410d34c954dee5807cf6323e1a /src/mesa/drivers/dri/i965/brw_wm_pass2.c | |
parent | 8f2a974cf2c9b6c00dfac11be4316a7d121dfbb4 (diff) |
i965: Move payload reg setup to compile, not lookup time.
Payload reg setup on gen6 depends more on the dispatch width as well
as the uses_depth, computes_depth, and other flags. That's something
we want to decide at compile time, not at cache lookup. As a bonus,
the fragment shader program cache lookup should be cheaper now that
there's less to compute for the hash key.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_wm_pass2.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_pass2.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c index 44e3953814..7b25dc11f1 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c @@ -76,7 +76,7 @@ static void init_registers( struct brw_wm_compile *c ) for (j = 0; j < c->grf_limit; j++) c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN; - for (j = 0; j < (c->key.nr_payload_regs + 1) / 2; j++) + for (j = 0; j < (c->nr_payload_regs + 1) / 2; j++) prealloc_reg(c, &c->payload.depth[j], i++); for (j = 0; j < c->nr_creg; j++) @@ -101,7 +101,7 @@ static void init_registers( struct brw_wm_compile *c ) assert(nr_interp_regs >= 1); - c->prog_data.first_curbe_grf = ALIGN(c->key.nr_payload_regs, 2); + c->prog_data.first_curbe_grf = ALIGN(c->nr_payload_regs, 2); c->prog_data.urb_read_length = nr_interp_regs * 2; c->prog_data.curb_read_length = c->nr_creg * 2; |