i965: Start building direct GLSL2 IR to 965 assembly codegen.

Our channel-expressions and vector-splitting changes now happen into a
private copy of the IR that we maintain for ourselves.  Uniform
assignment still happens by the core, so we continue using Mesa IR
generation not just for swrast fallbacks but also for uniform values
(since there's no storage for their contents other than
shader_program->FragmentProgram->Parameters->ParameterValues).  And
most importantly, at the moment no actual codegen is hooked up other
than emitting our favorite color to the framebuffer.

1 files changed, 16 insertions, 2 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index c1cf4db1ca..6699d0a73e 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -104,8 +104,22 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
    key->uses_kill = fp->UsesKill || ctx->Color.AlphaEnabled;
    key->is_glsl = bfp->isGLSL;
 
-   /* temporary sanity check assertion */
-   ASSERT(bfp->isGLSL == brw_wm_is_glsl(fp));
+   /* If using the fragment shader backend, the program is always
+    * 8-wide.
+    */
+   if (ctx->Shader.CurrentProgram) {
+      int i;
+
+      for (i = 0; i < ctx->Shader.CurrentProgram->_NumLinkedShaders; i++) {
+	 struct brw_shader *shader =
+	    (struct brw_shader *)ctx->Shader.CurrentProgram->_LinkedShaders[i];;
+
+	 if (shader->base.Type == GL_FRAGMENT_SHADER &&
+	     shader->ir != NULL) {
+	    key->is_glsl = GL_TRUE;
+	 }
+      }
+   }
 
    /* _NEW_DEPTH */
    key->stats_wm = intel->stats_wm;