diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-08-31 09:54:44 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-08-31 09:58:18 +0800 |
| commit | 24ff42e7d56ac489caeca6b5ffcc3091cc8194b5 (patch) | |
| tree | 67bdde14f87fb7aa7e2692ef219d184f456aac9e /src/mesa/drivers/dri/i965/gen6_cc.c | |
| parent | be7816f2b7f0b064a47fb3f101477ad5dba74017 (diff) | |
i965: fix depth test on sandybridge
This includes several corrections for fixing depth test on sandybridge.
Fix wrong bits definition in depth stencil state. Fix wrong order of
state buffer offset in 3DSTATE_CC_STATE_POINTERS command. Correctly use
buffer width parameter in depth buffer setting.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen6_cc.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_cc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c index f7acad6912..26f1070a16 100644 --- a/src/mesa/drivers/dri/i965/gen6_cc.c +++ b/src/mesa/drivers/dri/i965/gen6_cc.c @@ -267,9 +267,9 @@ static void upload_cc_state_pointers(struct brw_context *brw) BEGIN_BATCH(4); OUT_BATCH(CMD_3D_CC_STATE_POINTERS << 16 | (4 - 2)); - OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); OUT_RELOC(brw->cc.blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); ADVANCE_BATCH(); intel_batchbuffer_emit_mi_flush(intel->batch); |