summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri/i965/intel_context.c
diff options
context:
space:
mode:
authorHaihao Xiang <haihao.xiang@intel.com>2006-12-30 10:30:42 -0800
committerEric Anholt <eric@anholt.net>2006-12-30 10:30:42 -0800
commit3943d7f8b12370dd77dda66e70aa8f1fcd217f9f (patch)
tree9a0ebf8a6fc82854b84866b296d860b15306c82a /src/mesa/drivers/dri/i965/intel_context.c
parent8c180c72d5fed5f26f258759f9649fc647a764ff (diff)
Use the tiled flag in the sarea to determine region tiling.
This fixes mis-rendering if back/depth fail to get set up as tiled. While it probably won't ever be the case now that the pitch limits are loosened, this is still the right thing to do.
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_context.c')
-rw-r--r--src/mesa/drivers/dri/i965/intel_context.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index d13e287fa7..5e97e4d609 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -403,7 +403,7 @@ GLboolean intelInitContext( struct intel_context *intel,
intelScreen->cpp,
intelScreen->front.pitch / intelScreen->cpp,
intelScreen->height,
- GL_FALSE);
+ intelScreen->front.tiled != 0); /* 0: LINEAR */
intel->back_region =
@@ -414,7 +414,7 @@ GLboolean intelInitContext( struct intel_context *intel,
intelScreen->cpp,
intelScreen->back.pitch / intelScreen->cpp,
intelScreen->height,
- (INTEL_DEBUG & DEBUG_TILE) ? 0 : 1);
+ intelScreen->back.tiled != 0);
/* Still assuming front.cpp == depth.cpp
*
@@ -430,7 +430,7 @@ GLboolean intelInitContext( struct intel_context *intel,
intelScreen->cpp,
intelScreen->depth.pitch / intelScreen->cpp,
intelScreen->height,
- (INTEL_DEBUG & DEBUG_TILE) ? 0 : 1);
+ intelScreen->depth.tiled != 0);
intel_bufferobj_init( intel );
intel->batch = intel_batchbuffer_alloc( intel );