Merge branch 'master' of git+ssh://joukj@git.freedesktop.org/git/mesa/mesa

54 files changed, 615 insertions, 3246 deletions

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 9e4ff112dc..7e07bc9c1a 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -11,6 +11,7 @@ DRIVER_SOURCES = \
 	intel_buffer_objects.c \
 	intel_buffers.c \
 	intel_context.c \
+	intel_decode.c \
 	intel_ioctl.c \
 	intel_mipmap_tree.c \
 	intel_regions.c \
@@ -22,8 +23,6 @@ DRIVER_SOURCES = \
 	intel_tex.c \
 	intel_tex_layout.c \
 	intel_tex_validate.c \
-	brw_aub.c \
-	brw_aub_playback.c \
 	brw_cc.c \
 	brw_clip.c \
 	brw_clip_line.c \
@@ -77,6 +76,12 @@ DRIVER_SOURCES = \
 	brw_wm_state.c \
 	brw_wm_surface_state.c 
 
+SYMLINKS = \
+	server/i830_dri.h \
+	server/i830_common.h \
+	server/intel_dri.c \
+	server/intel.h
+
 C_SOURCES = \
 	$(COMMON_SOURCES) \
 	$(MINIGLX_SOURCES) \
@@ -88,6 +93,13 @@ DRIVER_DEFINES = -I../intel
 
 include ../Makefile.template
 
+intel_decode.o: ../intel/intel_decode.c
 intel_tex_layout.o: ../intel/intel_tex_layout.c
 
-symlinks:
+server:
+	mkdir -p server
+
+$(SYMLINKS): server
+	@[ -e $@ ] || ln -sf ../../i915/$@ server/
+
+symlinks: $(SYMLINKS)
diff --git a/src/mesa/drivers/dri/i965/brw_aub.c b/src/mesa/drivers/dri/i965/brw_aub.c
deleted file mode 100644
index f851a5b795..0000000000
--- a/src/mesa/drivers/dri/i965/brw_aub.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- Copyright (C) Intel Corp.  2006.  All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
- develop this 3D driver.
- 
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
- 
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial
- portions of the Software.
- 
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- 
- **********************************************************************/
- /*
-  * Authors:
-  *   Keith Whitwell <keith@tungstengraphics.com>
-  */
-
-#include "brw_context.h"
-#include "brw_aub.h"
-#include "intel_regions.h"
-#include <stdio.h>
-
-extern char *__progname;
-
-
-/* Registers to control page table
- */
-#define PGETBL_CTL       0x2020
-#define PGETBL_ENABLED   0x1
-
-#define NR_GTT_ENTRIES  65536	/* 256 mb */
-
-#define FAIL										\
-do {											\
-   fprintf(stderr, "failed to write aub data at %s/%d\n", __FUNCTION__, __LINE__);	\
-   exit(1);										\
-} while (0)
-
-
-/* Emit the headers at the top of each aubfile.  Initialize the GTT.
- */
-static void init_aubfile( FILE *aub_file )
-{   
-   struct aub_file_header fh;
-   struct aub_block_header bh;
-   unsigned int data;
-
-   static int nr;
-   
-   nr++;
-
-   /* Emit the aub header:
-    */
-   memset(&fh, 0, sizeof(fh));
-
-   fh.instruction_type = AUB_FILE_HEADER;
-   fh.minor = 0x0;
-   fh.major = 0x7;
-   memcpy(fh.application, __progname, sizeof(fh.application));
-   fh.day = (nr>>24) & 0xff;
-   fh.month = 0x0;
-   fh.year = 0x0;
-   fh.timezone = 0x0;
-   fh.second = nr & 0xff;
-   fh.minute = (nr>>8) & 0xff;
-   fh.hour = (nr>>16) & 0xff;
-   fh.comment_length = 0x0;   
-
-   if (fwrite(&fh, sizeof(fh), 1, aub_file) < 0) 
-      FAIL;
-         
-   /* Setup the GTT starting at main memory address zero (!):
-    */
-   memset(&bh, 0, sizeof(bh));
-   
-   bh.instruction_type = AUB_BLOCK_HEADER;
-   bh.operation = BH_MMI0_WRITE32;
-   bh.type = 0x0;
-   bh.address_space = ADDR_GTT;	/* ??? */
-   bh.general_state_type = 0x0;
-   bh.surface_state_type = 0x0;
-   bh.address = PGETBL_CTL;
-   bh.length = 0x4;
-
-   if (fwrite(&bh, sizeof(bh), 1, aub_file) < 0) 
-      FAIL;
-
-   data = 0x0 | PGETBL_ENABLED;
-
-   if (fwrite(&data, sizeof(data), 1, aub_file) < 0) 
-      FAIL;
-}
-
-
-static void init_aub_gtt( struct brw_context *brw,
-			  GLuint start_offset, 
-			  GLuint size )
-{
-   FILE *aub_file = brw->intel.aub_file;
-   struct aub_block_header bh;
-   unsigned int i;
-
-   assert(start_offset + size < NR_GTT_ENTRIES * 4096);
-
-
-   memset(&bh, 0, sizeof(bh));
-   
-   bh.instruction_type = AUB_BLOCK_HEADER;
-   bh.operation = BH_DATA_WRITE;
-   bh.type = 0x0;
-   bh.address_space = ADDR_MAIN;
-   bh.general_state_type = 0x0;
-   bh.surface_state_type = 0x0;
-   bh.address =  start_offset / 4096 * 4;
-   bh.length = size / 4096 * 4;
-
-   if (fwrite(&bh, sizeof(bh), 1, aub_file) < 0) 
-      FAIL;
-
-   for (i = 0; i < size / 4096; i++) {
-      GLuint data = brw->next_free_page | 1;
-
-      brw->next_free_page += 4096;
-
-      if (fwrite(&data, sizeof(data), 1, aub_file) < 0) 
-	 FAIL;
-   }
-
-}
-
-static void write_block_header( FILE *aub_file,
-				struct aub_block_header *bh,
-				const GLuint *data,
-				GLuint sz )
-{
-   sz = (sz + 3) & ~3;
-
-   if (fwrite(bh, sizeof(*bh), 1, aub_file) < 0) 
-      FAIL;
-
-   if (fwrite(data, sz, 1, aub_file) < 0) 
-      FAIL;
-
-   fflush(aub_file);
-}
-
-
-static void write_dump_bmp( FILE *aub_file,
-			    struct aub_dump_bmp *db )
-{
-   if (fwrite(db, sizeof(*db), 1, aub_file) < 0) 
-      FAIL;
-
-   fflush(aub_file);
-}
-
-
-
-static void brw_aub_gtt_data( struct intel_context *intel,
-			      GLuint offset,
-			      const void *data,
-			      GLuint sz,
-			      GLuint type,
-			      GLuint state_type )
-{
-   struct aub_block_header bh;
-
-   bh.instruction_type = AUB_BLOCK_HEADER;
-   bh.operation = BH_DATA_WRITE;
-   bh.type = type;
-   bh.address_space = ADDR_GTT;
-   bh.pad0 = 0;
-
-   if (type == DW_GENERAL_STATE) {
-      bh.general_state_type = state_type;
-      bh.surface_state_type = 0;
-   }
-   else {
-      bh.general_state_type = 0;
-      bh.surface_state_type = state_type;
-   }
-
-   bh.pad1 = 0;
-   bh.address = offset;
-   bh.length = sz;
-
-   write_block_header(intel->aub_file, &bh, data, sz);
-}
-
-
-
-static void brw_aub_gtt_cmds( struct intel_context *intel,
-			      GLuint offset,
-			      const void *data,
-			      GLuint sz )
-{
-   struct brw_context *brw = brw_context(&intel->ctx);
-   struct aub_block_header bh;   
-   GLuint type = CW_PRIMARY_RING_A;
-   
-
-   bh.instruction_type = AUB_BLOCK_HEADER;
-   bh.operation = BH_COMMAND_WRITE;
-   bh.type = type;
-   bh.address_space = ADDR_GTT;
-   bh.pad0 = 0;
-   bh.general_state_type = 0;
-   bh.surface_state_type = 0;
-   bh.pad1 = 0;
-   bh.address = offset;
-   bh.length = sz;
-
-   write_block_header(brw->intel.aub_file, &bh, data, sz);
-}
-
-static void brw_aub_dump_bmp( struct intel_context *intel,
-			      GLuint buffer )
-{
-   struct brw_context *brw = brw_context(&intel->ctx);
-   intelScreenPrivate *intelScreen = brw->intel.intelScreen;
-   struct aub_dump_bmp db;
-   GLuint format;
-
-   if (intelScreen->cpp == 4)
-      format = 0x7;
-   else
-      format = 0x3;
-
-
-   if (buffer == 0) {
-      db.instruction_type = AUB_DUMP_BMP;
-      db.xmin = 0;
-      db.ymin = 0;
-      db.format = format;
-      db.bpp = intelScreen->cpp * 8;
-      db.pitch = intelScreen->front.pitch / intelScreen->cpp;
-      db.xsize = intelScreen->width;
-      db.ysize = intelScreen->height;
-      db.addr = intelScreen->front.offset;
-      db.unknown = 0x0;		/* 4: xmajor tiled, 0: not tiled */
-
-      write_dump_bmp(brw->intel.aub_file, &db);
-   }
-   else {
-      db.instruction_type = AUB_DUMP_BMP;
-      db.xmin = 0;
-      db.ymin = 0;
-      db.format = format;
-      db.bpp = intel->back_region->cpp * 8;
-      db.pitch = intel->back_region->pitch;
-      db.xsize = intel->back_region->pitch;
-      db.ysize = intel->back_region->height;
-      db.addr = intelScreen->back.offset;
-      db.unknown = intel->back_region->tiled ? 0x4 : 0x0;
-
-      write_dump_bmp(brw->intel.aub_file, &db);
-   }
-}
-
-/* Attempt to prevent monster aubfiles by closing and reopening when
- * the state pools wrap.
- */
-static void brw_aub_wrap( struct intel_context *intel )
-{
-   struct brw_context *brw = brw_context(&intel->ctx);   
-   if (intel->aub_file) {
-      brw_aub_destroy(brw);
-      brw_aub_init(brw);
-   }
-   brw->wrap = 1;		/* ??? */
-}
-
-
-int brw_aub_init( struct brw_context *brw )
-{
-   struct intel_context *intel = &brw->intel;
-   intelScreenPrivate *intelScreen = intel->intelScreen;
-   char filename[80];
-   int val;
-   static int i = 0;
-
-   i++;
-
-   if (_mesa_getenv("INTEL_REPLAY"))
-      return 0;
-
-   if (_mesa_getenv("INTEL_AUBFILE")) {
-      val = snprintf(filename, sizeof(filename), "%s%d.aub", _mesa_getenv("INTEL_AUBFILE"), i%4);
-      _mesa_printf("--> Aub file: %s\n", filename);
-      brw->intel.aub_file = fopen(filename, "w");
-   }
-   else if (_mesa_getenv("INTEL_AUB")) {
-      val = snprintf(filename, sizeof(filename), "%s.aub", __progname);
-      if (val < 0 || val > sizeof(filename)) 
-	 strcpy(filename, "default.aub");   
-   
-      _mesa_printf("--> Aub file: %s\n", filename);
-      brw->intel.aub_file = fopen(filename, "w");
-   }
-   else {
-      return 0;
-   }
-
-   if (!brw->intel.aub_file) {
-      _mesa_printf("couldn't open aubfile\n");
-      exit(1);
-   }
-
-   brw->intel.vtbl.aub_commands = brw_aub_gtt_cmds;
-   brw->intel.vtbl.aub_dump_bmp = brw_aub_dump_bmp;
-   brw->intel.vtbl.aub_gtt_data = brw_aub_gtt_data;
-   brw->intel.vtbl.aub_wrap = brw_aub_wrap;
-   
-   init_aubfile(brw->intel.aub_file);
-
-   /* The GTT is located starting address zero in main memory.  Pages
-    * to populate the gtt start after this point.
-    */
-   brw->next_free_page = (NR_GTT_ENTRIES * 4 + 4095) & ~4095;
-
-   /* More or less correspond with all the agp regions mapped by the
-    * driver:
-    */
-   init_aub_gtt(brw, 0, 4096*4); /* so new fulsim doesn't crash */
-   init_aub_gtt(brw, intelScreen->front.offset, intelScreen->back.size);
-   init_aub_gtt(brw, intelScreen->back.offset, intelScreen->back.size);
-   init_aub_gtt(brw, intelScreen->depth.offset, intelScreen->back.size);
-   init_aub_gtt(brw, intelScreen->tex.offset, intelScreen->tex.size);
-
-   return 0;
-}
-
-void brw_aub_destroy( struct brw_context *brw )
-{
-   if (brw->intel.aub_file) {
-      fclose(brw->intel.aub_file);
-      brw->intel.aub_file = NULL;
-   }
-}
diff --git a/src/mesa/drivers/dri/i965/brw_aub.h b/src/mesa/drivers/dri/i965/brw_aub.h
deleted file mode 100644
index 198e36dc3c..0000000000
--- a/src/mesa/drivers/dri/i965/brw_aub.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- Copyright (C) Intel Corp.  2006.  All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
- develop this 3D driver.
- 
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
- 
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial
- portions of the Software.
- 
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- 
- **********************************************************************/
- /*
-  * Authors:
-  *   Keith Whitwell <keith@tungstengraphics.com>
-  */
-
-#ifndef BRW_AUB_H
-#define BRW_AUB_H
-
-struct aub_file_header {
-   unsigned int instruction_type;
-   unsigned int pad0:16;
-   unsigned int minor:8;
-   unsigned int major:8;
-   unsigned char application[8*4];
-   unsigned int day:8;
-   unsigned int month:8;
-   unsigned int year:16;
-   unsigned int timezone:8;
-   unsigned int second:8;
-   unsigned int minute:8;
-   unsigned int hour:8;
-   unsigned int comment_length:16;   
-   unsigned int pad1:16;
-};
-
-struct aub_block_header {
-   unsigned int instruction_type;
-   unsigned int operation:8;
-   unsigned int type:8;
-   unsigned int address_space:8;
-   unsigned int pad0:8;
-   unsigned int general_state_type:8;
-   unsigned int surface_state_type:8;
-   unsigned int pad1:16;
-   unsigned int address;
-   unsigned int length;
-};
-
-struct aub_dump_bmp {
-   unsigned int instruction_type;
-   unsigned int xmin:16;
-   unsigned int ymin:16;
-   unsigned int pitch:16;
-   unsigned int bpp:8;
-   unsigned int format:8;
-   unsigned int xsize:16;
-   unsigned int ysize:16;
-   unsigned int addr;
-   unsigned int unknown;
-};
-
-enum bh_operation {
-   BH_COMMENT,
-   BH_DATA_WRITE,
-   BH_COMMAND_WRITE,
-   BH_MMI0_WRITE32,
-   BH_END_SCENE,
-   BH_CONFIG_MEMORY_MAP,
-   BH_MAX_OPERATION
-};
-
-enum command_write_type {
-   CW_HWB_RING = 1,
-   CW_PRIMARY_RING_A,
-   CW_PRIMARY_RING_B,		/* XXX - disagreement with listaub! */
-   CW_PRIMARY_RING_C,
-   CW_MAX_TYPE
-};
-
-enum data_write_type {
-   DW_NOTYPE,
-   DW_BATCH_BUFFER,
-   DW_BIN_BUFFER,
-   DW_BIN_POINTER_LIST,
-   DW_SLOW_STATE_BUFFER,
-   DW_VERTEX_BUFFER,
-   DW_2D_MAP,
-   DW_CUBE_MAP,
-   DW_INDIRECT_STATE_BUFFER,
-   DW_VOLUME_MAP,
-   DW_1D_MAP,
-   DW_CONSTANT_BUFFER,
-   DW_CONSTANT_URB_ENTRY,
-   DW_INDEX_BUFFER,
-   DW_GENERAL_STATE,
-   DW_SURFACE_STATE,
-   DW_MEDIA_OBJECT_INDIRECT_DATA,
-   DW_MAX_TYPE
-};
-
-enum data_write_general_state_type {
-   DWGS_NOTYPE,
-   DWGS_VERTEX_SHADER_STATE,
-   DWGS_GEOMETRY_SHADER_STATE ,
-   DWGS_CLIPPER_STATE,
-   DWGS_STRIPS_FANS_STATE,
-   DWGS_WINDOWER_IZ_STATE,
-   DWGS_COLOR_CALC_STATE,
-   DWGS_CLIPPER_VIEWPORT_STATE,	/* was 0x7 */
-   DWGS_STRIPS_FANS_VIEWPORT_STATE,
-   DWGS_COLOR_CALC_VIEWPORT_STATE, /* was 0x9 */
-   DWGS_SAMPLER_STATE,
-   DWGS_KERNEL_INSTRUCTIONS,
-   DWGS_SCRATCH_SPACE,
-   DWGS_SAMPLER_DEFAULT_COLOR,
-   DWGS_INTERFACE_DESCRIPTOR,
-   DWGS_VLD_STATE,
-   DWGS_VFE_STATE,
-   DWGS_MAX_TYPE
-};
-
-enum data_write_surface_state_type {
-   DWSS_NOTYPE,
-   DWSS_BINDING_TABLE_STATE,
-   DWSS_SURFACE_STATE,
-   DWSS_MAX_TYPE
-};
-
-enum memory_map_type {
-   MM_DEFAULT,
-   MM_DYNAMIC,
-   MM_MAX_TYPE
-};
-
-enum address_space {
-   ADDR_GTT,
-   ADDR_LOCAL,
-   ADDR_MAIN,
-   ADDR_MAX
-};
-
-
-#define AUB_FILE_HEADER 0xe085000b
-#define AUB_BLOCK_HEADER 0xe0c10003
-#define AUB_DUMP_BMP 0xe09e0004
-
-struct brw_context;
-struct intel_context;
-
-int brw_aub_init( struct brw_context *brw );
-void brw_aub_destroy( struct brw_context *brw );
-
-int brw_playback_aubfile(struct brw_context *brw,
-			 const char *filename);
-
-#endif
diff --git a/src/mesa/drivers/dri/i965/brw_aub_playback.c b/src/mesa/drivers/dri/i965/brw_aub_playback.c
deleted file mode 100644
index 2433d50c11..0000000000
--- a/src/mesa/drivers/dri/i965/brw_aub_playback.c
+++ /dev/null
@@ -1,443 +0,0 @@
-
-#include <stdio.h>
-#include <sys/mman.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <unistd.h>
-#include <fcntl.h>
-
-#include "brw_aub.h"
-#include "brw_defines.h"
-#include "brw_context.h"
-#include "intel_ioctl.h"
-#include "bufmgr.h"
-
-struct aub_state {
-   struct intel_context *intel;
-   const char *map;
-   unsigned int csr;
-   unsigned int sz;
-};
-
-
-static int gobble( struct aub_state *s, int size )
-{
-   if (s->csr + size > s->sz) {
-      _mesa_printf("EOF in %s\n", __FUNCTION__);
-      return 1;
-   }
-
-   s->csr += size;
-   return 0;
-}
-
-static void flush_and_fence( struct aub_state *s )
-{
-   struct intel_context *intel = s->intel;
-   GLuint buf[2];
-
-   buf[0] = intel->vtbl.flush_cmd();
-   buf[1] = 0;
-
-   intel_cmd_ioctl(intel, (char *)&buf, sizeof(buf));
-      
-   intelWaitIrq( intel, intelEmitIrqLocked( intel ));
-}
-
-static void flush_cmds( struct aub_state *s,
-			const void *data,
-			int len )
-{
-   DBG("%s %d\n", __FUNCTION__, len);
-
-   if (len & 0x4) {
-      unsigned int *tmp = malloc(len + 4);
-      DBG("padding to octword\n");
-      memcpy(tmp, data, len);
-      tmp[len/4] = MI_NOOP;
-      flush_cmds(s, tmp, len+4);
-      free(tmp);
-      return;
-   }
-
-   /* For ring data, just send off immediately via an ioctl.
-    * This differs slightly from how the stream was executed
-    * initially as this would have been a batchbuffer.
-    */
-   intel_cmd_ioctl(s->intel, (void *)data, len);
-
-   if (1)
-      flush_and_fence(s);
-}
-
-static const char *pstrings[] = {
-   "none",
-   "POINTLIST",
-   "LINELIST",
-   "LINESTRIP",
-   "TRILIST",
-   "TRISTRIP",
-   "TRIFAN",
-   "QUADLIST",
-   "QUADSTRIP",
-   "LINELIST_ADJ",
-   "LINESTRIP_ADJ",
-   "TRILIST_ADJ",
-   "TRISTRIP_ADJ",
-   "TRISTRIP_REVERSE",
-   "POLYGON",
-   "RECTLIST",
-   "LINELOOP",
-   "POINTLIST_BF",
-   "LINESTRIP_CONT",
-   "LINESTRIP_BF",
-   "LINESTRIP_CONT_BF",
-   "TRIFAN_NOSTIPPLE",
-};
-
-static void do_3d_prim( struct aub_state *s,
-			const void *data,
-			int len )
-{
-   struct brw_3d_primitive prim;
-   const struct brw_3d_primitive *orig = data;
-   int i;
-
-   assert(len == sizeof(prim));
-   memcpy(&prim, data, sizeof(prim));
-
-#define START 0
-#define BLOCK (12*28)
-
-   if (orig->verts_per_instance < BLOCK)
-      flush_cmds(s, &prim, sizeof(prim));
-   else {
-      for (i = START; i + BLOCK < orig->verts_per_instance; i += BLOCK/2) {
-	 prim.start_vert_location = i;
-	 prim.verts_per_instance = BLOCK;
-	 _mesa_printf("%sprim %d/%s verts %d..%d (of %d)\n", 
-		      prim.header.indexed ? "INDEXED " : "",
-		      prim.header.topology, pstrings[prim.header.topology%16],
-		      prim.start_vert_location, 
-		      prim.start_vert_location + prim.verts_per_instance,
-		      orig->verts_per_instance);
-	 flush_cmds(s, &prim, sizeof(prim));
-      }
-   }
-}
-
-
-
-static struct {
-   int cmd;
-   const char *name;
-   int has_length;
-} cmd_info[] = {
-   { 0, "NOOP", 0 },
-   { 0x5410, "XY_COLOR_BLT_RGB", 1 },
-   { 0x5430, "XY_COLOR_BLT_RGBA", 1 },
-   { 0x54d0, "XY_SRC_COPY_BLT_RGB", 1 },
-   { 0x54f0, "XY_SRC_COPY_BLT_RGBA", 1 },
-   { CMD_URB_FENCE, "URB_FENCE",  1 },
-   { CMD_CONST_BUFFER_STATE, "CONST_BUFFER_STATE",  1 },
-   { CMD_CONST_BUFFER, "CONST_BUFFER",  1 },
-   { CMD_STATE_BASE_ADDRESS, "STATE_BASE_ADDRESS",  1 },
-   { CMD_STATE_INSN_POINTER, "STATE_INSN_POINTER",  1 },
-   { CMD_PIPELINE_SELECT, "PIPELINE_SELECT", 0, },
-   { CMD_PIPELINED_STATE_POINTERS, "PIPELINED_STATE_POINTERS", 1 },
-   { CMD_BINDING_TABLE_PTRS, "BINDING_TABLE_PTRS", 1 },
-   { CMD_VERTEX_BUFFER, "VERTEX_BUFFER", 1 },
-   { CMD_VERTEX_ELEMENT, "VERTEX_ELEMENT", 1 },
-   { CMD_INDEX_BUFFER, "INDEX_BUFFER", 1 },
-   { CMD_VF_STATISTICS, "VF_STATISTICS", 0 },
-   { CMD_DRAW_RECT, "DRAW_RECT", 1 },
-   { CMD_BLEND_CONSTANT_COLOR, "BLEND_CONSTANT_COLOR", 1 },
-   { CMD_CHROMA_KEY, "CHROMA_KEY", 1 },
-   { CMD_DEPTH_BUFFER, "DEPTH_BUFFER", 1 },
-   { CMD_POLY_STIPPLE_OFFSET, "POLY_STIPPLE_OFFSET", 1 },
-   { CMD_POLY_STIPPLE_PATTERN, "POLY_STIPPLE_PATTERN", 1 },
-   { CMD_LINE_STIPPLE_PATTERN, "LINE_STIPPLE_PATTERN", 1 },
-   { CMD_GLOBAL_DEPTH_OFFSET_CLAMP, "GLOBAL_DEPTH_OFFSET_CLAMP", 1 },
-   { CMD_PIPE_CONTROL, "PIPE_CONTROL", 1 },
-   { CMD_MI_FLUSH, "MI_FLUSH", 0 },
-   { CMD_3D_PRIM, "3D_PRIM", 1 },
-};
-
-#define NR_CMDS (sizeof(cmd_info)/sizeof(cmd_info[0]))
-
-
-static int find_command( unsigned int cmd )
-{
-   int i;
-
-   for (i = 0; i < NR_CMDS; i++) 
-      if (cmd == cmd_info[i].cmd) 
-	 return i;
-
-   return -1;
-}
-
-
-
-static int parse_commands( struct aub_state *s,
-			   const unsigned int *data,
-			   int len )
-{
-   while (len) {
-      int cmd = data[0] >> 16;
-      int dwords;
-      int i;
-
-      i = find_command(cmd);
-
-      if (i < 0) {
-	 _mesa_printf("couldn't find info for cmd %x\n", cmd);
-	 return 1;
-      }
-
-      if (cmd_info[i].has_length)
-	 dwords = (data[0] & 0xff) + 2;
-      else
-	 dwords = 1;
-
-      _mesa_printf("%s (%d dwords) 0x%x\n", cmd_info[i].name, dwords, data[0]);
-
-      if (len < dwords * 4) {
-	 _mesa_printf("EOF in %s (%d bytes)\n", __FUNCTION__, len);
-	 return 1;
-      }
-
-
-      if (0 && cmd == CMD_3D_PRIM)
-	 do_3d_prim(s, data, dwords * 4);
-      else
-	 flush_cmds(s, data, dwords * 4);
-
-      data += dwords;
-      len -= dwords * 4;
-   }
-
-   return 0;
-}
-
-
-
-static void parse_data_write( struct aub_state *s,
-			     const struct aub_block_header *bh,
-			     void *dest,
-			     const unsigned int *data,
-			     int len )
-{
-   switch (bh->type) {
-   case DW_GENERAL_STATE:
-      switch (bh->general_state_type) {
-      case DWGS_VERTEX_SHADER_STATE: {
-	 struct brw_vs_unit_state vs;
-	 assert(len == sizeof(vs));
-
-	 _mesa_printf("DWGS_VERTEX_SHADER_STATE\n");
-	 memcpy(&vs, data, sizeof(vs));
-
-/* 	 vs.vs6.vert_cache_disable = 1;  */
-/*  	 vs.thread4.max_threads = 4;  */
-
-	 memcpy(dest, &vs, sizeof(vs));
-	 return;
-      }
-      case DWGS_CLIPPER_STATE: {
-	 struct brw_clip_unit_state clip;
-	 assert(len == sizeof(clip));
-
-	 _mesa_printf("DWGS_CLIPPER_STATE\n");
-	 memcpy(&clip, data, sizeof(clip));
-
-/* 	 clip.thread4.max_threads = 0; */
-/*   	 clip.clip5.clip_mode = BRW_CLIPMODE_REJECT_ALL;   */
-
-	 memcpy(dest, &clip, sizeof(clip));
-	 return;
-      }
-
-      case DWGS_NOTYPE:
-      case DWGS_GEOMETRY_SHADER_STATE:
-      case DWGS_STRIPS_FANS_STATE:
-	 break;
-
-      case DWGS_WINDOWER_IZ_STATE: {
-	    struct brw_wm_unit_state wm;
-	    assert(len == sizeof(wm));
-
-	    _mesa_printf("DWGS_WINDOWER_IZ_STATE\n");
-	    memcpy(&wm, data, sizeof(wm));
-
-/* 	    wm.wm5.max_threads = 10; */
-
-	    memcpy(dest, &wm, sizeof(wm));
-	    return;
-	 }
-
-      case DWGS_COLOR_CALC_STATE:
-      case DWGS_CLIPPER_VIEWPORT_STATE:
-      case DWGS_STRIPS_FANS_VIEWPORT_STATE:
-      case DWGS_COLOR_CALC_VIEWPORT_STATE:
-      case DWGS_SAMPLER_STATE:
-      case DWGS_KERNEL_INSTRUCTIONS:
-      case DWGS_SCRATCH_SPACE:
-      case DWGS_SAMPLER_DEFAULT_COLOR:
-      case DWGS_INTERFACE_DESCRIPTOR:
-      case DWGS_VLD_STATE:
-      case DWGS_VFE_STATE:
-      default:
-	 break;
-      }
-      break;
-   case DW_SURFACE_STATE:
-      break;
-   case DW_1D_MAP:
-   case DW_2D_MAP:
-   case DW_CUBE_MAP:
-   case DW_VOLUME_MAP:
-   case DW_CONSTANT_BUFFER:
-   case DW_CONSTANT_URB_ENTRY:
-   case DW_VERTEX_BUFFER:
-   case DW_INDEX_BUFFER:
-   default:
-      break;
-   }
-
-   memcpy(dest, data, len);
-}
-
-
-/* In order to work, the memory layout has to be the same as the X
- * server which created the aubfile.
- */
-static int parse_block_header( struct aub_state *s )
-{
-   struct aub_block_header *bh = (struct aub_block_header *)(s->map + s->csr);
-   void *data = (void *)(bh + 1);
-   unsigned int len = (bh->length + 3) & ~3;
-
-   _mesa_printf("block header at 0x%x\n", s->csr);
-
-   if (s->csr + len + sizeof(*bh) > s->sz) {
-      _mesa_printf("EOF in data in %s\n", __FUNCTION__);
-      return 1;
-   }
-
-   if (bh->address_space == ADDR_GTT) {
-
-      switch (bh->operation)
-      {
-      case BH_DATA_WRITE: {
-	 void *dest = bmFindVirtual( s->intel, bh->address, len );
-	 if (dest == NULL) {
-	    _mesa_printf("Couldn't find virtual address for offset %x\n", bh->address);
-	    return 1;
-	 }
-
-#if 1
-	 parse_data_write(s, bh, dest, data, len);
-#else
-	 memcpy(dest, data, len);
-#endif
-	 break;
-      }
-      case BH_COMMAND_WRITE:
-#if 0
-	 intel_cmd_ioctl(s->intel, (void *)data, len);
-#else
-	 if (parse_commands(s, data, len) != 0)
-	    _mesa_printf("parse_commands failed\n");
-#endif
-	 break;
-      default:
-	 break;
-      }
-   }
-
-   s->csr += sizeof(*bh) + len;
-   return 0;
-}
-
-
-#define AUB_FILE_HEADER 0xe085000b
-#define AUB_BLOCK_HEADER 0xe0c10003
-#define AUB_DUMP_BMP 0xe09e0004
-
-int brw_playback_aubfile(struct brw_context *brw,
-			 const char *filename)
-{
-   struct intel_context *intel = &brw->intel;
-   struct aub_state state;
-   struct stat sb;
-   int fd;
-   int retval = 0;
-
-   state.intel = intel;
-
-   fd = open(filename, O_RDONLY, 0);
-   if (fd < 0) {
-      _mesa_printf("couldn't open aubfile: %s\n", filename);
-      return 1;
-   }
-
-   if (fstat(fd, &sb) != 0) {
-      _mesa_printf("couldn't open %s\n", filename);
-      return 1;
-   }
-
-   state.csr = 0;
-   state.sz = sb.st_size;
-   state.map = mmap(NULL, sb.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
-   
-   if (state.map == NULL) {
-      _mesa_printf("couldn't mmap %s\n", filename);
-      return 1;
-   }
-
-   LOCK_HARDWARE(intel); 
-   {
-      /* Make sure we don't confuse anything that might happen to be
-       * going on with the hardware:
-       */
-/*       bmEvictAll(intel); */
-/*       intel->vtbl.lost_hardware(intel); */
-      
-
-      /* Replay the aubfile item by item: 
-       */
-      while (retval == 0 && 
-	     state.csr != state.sz) {
-	 unsigned int insn = *(unsigned int *)(state.map + state.csr);
-
-	 switch (insn) {
-	 case AUB_FILE_HEADER:
-	    retval = gobble(&state, sizeof(struct aub_file_header));
-	    break;
-	 
-	 case AUB_BLOCK_HEADER:   
-	    retval = parse_block_header(&state);
-	    break;
-	 
-	 case AUB_DUMP_BMP:
-	    retval = gobble(&state, sizeof(struct aub_dump_bmp));
-	    break;
-	 
-	 default:
-	    _mesa_printf("unknown instruction %x\n", insn);
-	    retval = 1;
-	    break;
-	 }
-      }
-   }
-   UNLOCK_HARDWARE(intel);
-   return retval;
-}
-
-
-
-
-
-
-		  
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
index 3bec153075..8287fd9edf 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -212,6 +212,10 @@ static void upload_clip_prog( struct brw_context *brw )
 	    }
 	 }
 
+    if (brw->attribs.Polygon->BackMode != GL_FILL ||
+        brw->attribs.Polygon->FrontMode != GL_FILL)
+        key.do_unfilled = 1;
+
 	 /* Most cases the fixed function units will handle.  Cases where
 	  * one or more polygon faces are unfilled will require help:
 	  */
diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c
index 83182270ea..9ad00676d4 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_line.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_line.c
@@ -130,6 +130,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
    struct brw_instruction *plane_loop;
    struct brw_instruction *plane_active;
    struct brw_instruction *is_negative;
+   struct brw_instruction *is_neg2;
    struct brw_instruction *not_culled;
    struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UD);
 
@@ -146,6 +147,13 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
    brw_clip_init_planes(c);
    brw_clip_init_clipmask(c);
 
+   /* -ve rhw workaround */
+   brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
+   brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
+	   brw_imm_ud(1<<20));
+   brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
+   brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
    plane_loop = brw_DO(p, BRW_EXECUTE_1);
    {
       /* if (planemask & 1)
@@ -183,13 +191,20 @@ static void clip_and_emit_line( struct brw_clip_compile *c )
 	    /* Coming back in.  We know that both cannot be negative
 	     * because the line would have been culled in that case.
 	     */
-	    brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
-	    brw_math_invert(p, c->reg.t, c->reg.t);
-	    brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
 
-	    brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 );
-	    brw_MOV(p, c->reg.t0, c->reg.t);
-	    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+	    /* If both are positive, do nothing */
+             brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0));
+             is_neg2 = brw_IF(p, BRW_EXECUTE_1);
+             {
+		brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
+		brw_math_invert(p, c->reg.t, c->reg.t);
+		brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
+
+		brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 );
+		brw_MOV(p, c->reg.t0, c->reg.t);
+		brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+	     }
+	     brw_ENDIF(p, is_neg2);
 	 }
 	 brw_ENDIF(p, is_negative);	 
       }
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 1e6d6fa176..ae46d7a86e 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -55,7 +55,7 @@ static void upload_clip_unit( struct brw_context *brw )
    /* BRW_NEW_URB_FENCE */
    clip.thread4.nr_urb_entries = brw->urb.nr_clip_entries; 
    clip.thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
-   clip.thread4.max_threads = 0; /* Hmm, maybe the max is 1 or 2 threads */
+   clip.thread4.max_threads = 1; /* 2 threads */
 
    if (INTEL_DEBUG & DEBUG_STATS)
       clip.thread4.stats_enable = 1; 
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index f62b02cedf..b7d30bb0c4 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c
@@ -42,6 +42,20 @@
 #include "brw_util.h"
 #include "brw_clip.h"
 
+static struct brw_reg get_tmp( struct brw_clip_compile *c )
+{
+   struct brw_reg tmp = brw_vec4_grf(c->last_tmp, 0);
+
+   if (++c->last_tmp > c->prog_data.total_grf)
+      c->prog_data.total_grf = c->last_tmp;
+
+   return tmp;
+}
+
+static void release_tmps( struct brw_clip_compile *c )
+{
+   c->last_tmp = c->first_tmp;
+}
 
 
 void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, 
@@ -435,15 +449,102 @@ static void maybe_do_clip_tri( struct brw_clip_compile *c )
    brw_ENDIF(p, do_clip);
 }
 
-
+static void brw_clip_test( struct brw_clip_compile *c )
+{
+    struct brw_reg t = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
+    struct brw_reg t1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
+    struct brw_reg t2 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
+    struct brw_reg t3 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD);
+
+    struct brw_reg v0 = get_tmp(c);
+    struct brw_reg v1 = get_tmp(c);
+    struct brw_reg v2 = get_tmp(c);
+
+    struct brw_indirect vt0 = brw_indirect(0, 0);
+    struct brw_indirect vt1 = brw_indirect(1, 0);
+    struct brw_indirect vt2 = brw_indirect(2, 0);
+
+    struct brw_compile *p = &c->func;
+
+    brw_MOV(p, get_addr_reg(vt0), brw_address(c->reg.vertex[0]));
+    brw_MOV(p, get_addr_reg(vt1), brw_address(c->reg.vertex[1]));
+    brw_MOV(p, get_addr_reg(vt2), brw_address(c->reg.vertex[2]));
+    brw_MOV(p, v0, deref_4f(vt0, c->offset[VERT_RESULT_HPOS]));
+    brw_MOV(p, v1, deref_4f(vt1, c->offset[VERT_RESULT_HPOS]));
+    brw_MOV(p, v2, deref_4f(vt2, c->offset[VERT_RESULT_HPOS]));
+
+    /* test nearz, xmin, ymin plane */
+    brw_CMP(p, t1, BRW_CONDITIONAL_LE, negate(v0), get_element(v0, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, t2, BRW_CONDITIONAL_LE, negate(v1), get_element(v1, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, t3, BRW_CONDITIONAL_LE, negate(v2), get_element(v2, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_XOR(p, t, t1, t2);
+    brw_XOR(p, t1, t2, t3);
+    brw_OR(p, t, t, t1);
+
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 0), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<5)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 1), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<3)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 2), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<1)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
+    /* test farz, xmax, ymax plane */
+    brw_CMP(p, t1, BRW_CONDITIONAL_L, v0, get_element(v0, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, t2, BRW_CONDITIONAL_L, v1, get_element(v1, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, t3, BRW_CONDITIONAL_L, v2, get_element(v2, 3)); 
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
+    brw_XOR(p, t, t1, t2);
+    brw_XOR(p, t1, t2, t3);
+    brw_OR(p, t, t, t1);
+
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 0), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<4)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 1), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<2)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+    brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_NZ, 
+	    get_element(t, 2), brw_imm_ud(0));
+    brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud((1<<0)));
+    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+
+    release_tmps(c);
+}
 
 
 void brw_emit_tri_clip( struct brw_clip_compile *c )
 {
+   struct brw_instruction *neg_rhw;
+   struct brw_compile *p = &c->func;
    brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6);
    brw_clip_tri_init_vertices(c);
    brw_clip_init_clipmask(c);
 
+   /* if -ve rhw workaround bit is set, 
+      do cliptest */
+   brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
+   brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), 
+	   brw_imm_ud(1<<20));
+   neg_rhw = brw_IF(p, BRW_EXECUTE_1); 
+   {
+       brw_clip_test(c);
+   }
+   brw_ENDIF(p, neg_rhw);
+
    /* Can't push into do_clip_tri because with polygon (or quad)
     * flatshading, need to apply the flatshade here because we don't
     * respect the PV when converting to trifan for emit:
@@ -462,6 +563,3 @@ void brw_emit_tri_clip( struct brw_clip_compile *c )
     */
    brw_clip_kill_thread(c);
 }
-
-
-
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c
index 19bef19801..c37bfeb1ce 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -272,6 +272,7 @@ void brw_clip_kill_thread(struct brw_clip_compile *c)
 
 
 
+
 struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c )
 {
    return brw_address(c->reg.fixed_planes);
@@ -327,8 +328,7 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
    
    /* Shift so that lowest outcode bit is rightmost: 
     */
-   brw_MOV(p, c->reg.planemask, incoming);
-   brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(26));
+   brw_SHR(p, c->reg.planemask, incoming, brw_imm_ud(26));
 
    if (c->key.nr_userclip) {
       struct brw_reg tmp = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UD);
@@ -342,13 +342,5 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
       
       release_tmp(c, tmp);
    }
-
-   /* Test for -ve rhw workaround 
-    */
-   brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
-   brw_AND(p, vec1(brw_null_reg()), incoming, brw_imm_ud(1<<20));
-   brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
-   brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 397a9bd3f5..0ccdd8a661 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -31,7 +31,6 @@
 
 
 #include "brw_context.h"
-#include "brw_aub.h"
 #include "brw_defines.h"
 #include "brw_draw.h"
 #include "brw_vs.h"
@@ -135,8 +134,6 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
 
    driInitExtensions( ctx, brw_extensions, GL_FALSE );
 
-   brw_aub_init( brw );
-
    brw_init_attribs( brw );
    brw_init_metaops( brw );
    brw_init_state( brw );
@@ -156,14 +153,6 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis,
 
    brw_FrameBufferTexInit( brw );
 
-   {
-      const char *filename = getenv("INTEL_REPLAY");
-      if (filename) {
-	 brw_playback_aubfile(brw, filename);
-	 exit(0);
-      }
-   }
-
    return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 08fdc54520..aa797b72ce 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -277,9 +277,6 @@ struct brw_cache {
    GLuint key_size;		/* for fixed-size keys */
    GLuint aux_size;
 
-   GLuint aub_type;
-   GLuint aub_sub_type;
-   
    GLuint last_addr;			/* offset of active item */
 };
 
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 3f0aaa1f86..d3c88c1dca 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -42,7 +42,6 @@
 #include "brw_defines.h"
 #include "brw_state.h"
 #include "brw_util.h"
-#include "brw_aub.h"
 
 
 /* Partition the CURBE between the various users of constant values:
@@ -90,7 +89,7 @@ static void calculate_curbe_offsets( struct brw_context *brw )
     */
    if (nr_fp_regs > brw->curbe.wm_size ||
        nr_vp_regs > brw->curbe.vs_size ||
-       nr_clip_regs > brw->curbe.clip_size ||
+       nr_clip_regs != brw->curbe.clip_size ||
        (total_regs < brw->curbe.total_size / 4 &&
 	brw->curbe.total_size > 16)) {
 
@@ -315,13 +314,11 @@ static void upload_constant_buffer(struct brw_context *brw)
 
       /* Copy data to the buffer:
        */
-      bmBufferSubDataAUB(&brw->intel,
-			 pool->buffer,
-			 brw->curbe.gs_offset, 
-			 bufsz, 
-			 buf,
-			 DW_CONSTANT_BUFFER,
-			 0);
+      bmBufferSubData(&brw->intel,
+		      pool->buffer,
+		      brw->curbe.gs_offset,
+		      bufsz,
+		      buf);
    }
 
    /* TODO: only emit the constant_buffer packet when necessary, ie:
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e8f878a701..9bb7d2f703 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -240,6 +240,8 @@
 #define BRW_FRONTWINDING_CW      0
 #define BRW_FRONTWINDING_CCW     1
 
+#define BRW_SPRITE_POINT_ENABLE  16
+
 #define BRW_INDEX_BYTE     0
 #define BRW_INDEX_WORD     1
 #define BRW_INDEX_DWORD    2
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 0c64d7e756..b23b357988 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -36,7 +36,6 @@
 #include "brw_draw.h"
 #include "brw_defines.h"
 #include "brw_context.h"
-#include "brw_aub.h"
 #include "brw_state.h"
 #include "brw_fallback.h"
 
@@ -331,6 +330,7 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx,
       else {
 	 /* Otherwise, explicitly do the cliprects at this point:
 	  */
+          GLuint nprims = 0;
 	 for (j = 0; j < brw->intel.numClipRects; j++) {
 	    brw_emit_cliprect(brw, &brw->intel.pClipRects[j]);
 
@@ -338,6 +338,11 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx,
 	     */
 	    for (i = 0; i < nr_prims; i++) {
 	       brw_emit_prim(brw, &prim[i]);   
+
+          if (++nprims == VBO_MAX_PRIM) {
+              intel_batchbuffer_flush(brw->intel.batch);
+              nprims = 0;
+          }
 	    }
 	 }
       }
@@ -462,11 +467,6 @@ void brw_draw_prims( GLcontext *ctx,
        _swsetup_Wakeup(ctx);
       _tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
    }
-
-   if (intel->aub_file && (INTEL_DEBUG & DEBUG_SYNC)) {
-      intelFinish( &intel->ctx );
-      intel->aub_wrap = 1;
-   }
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 6150cac4aa..fc2e3035af 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -36,7 +36,6 @@
 #include "brw_draw.h"
 #include "brw_defines.h"
 #include "brw_context.h"
-#include "brw_aub.h"
 #include "brw_state.h"
 #include "brw_fallback.h"
 
@@ -593,6 +592,28 @@ void brw_upload_indices( struct brw_context *brw,
 				 ib_size,
 				 index_buffer->ptr,
 				 bufferobj);
+   } else {
+       if (((1 << get_index_type(index_buffer->type)) - 1) & offset) {
+           struct gl_buffer_object *vbo;
+           GLuint voffset;
+           GLubyte *map = ctx->Driver.MapBuffer(ctx,
+                                                GL_ELEMENT_ARRAY_BUFFER_ARB,
+                                                GL_DYNAMIC_DRAW_ARB,
+                                                bufferobj);
+           map += offset;
+           get_space(brw, ib_size, &vbo, &voffset);
+           
+           ctx->Driver.BufferSubData(ctx,
+                                     GL_ELEMENT_ARRAY_BUFFER_ARB,
+                                     voffset,
+                                     ib_size,
+                                     map,
+                                     vbo);
+           ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER_ARB, bufferobj);
+
+           bufferobj = vbo;
+           offset = voffset;
+       }
    }
 
    /* Emit the indexbuffer packet:
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 752fe49bcb..8e8fea48e9 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -29,15 +29,14 @@
   *   Keith Whitwell <keith@tungstengraphics.com>
   */
   
+#include "main/imports.h"
+#include "main/enums.h"
 #include "shader/prog_parameter.h"
-#include "brw_context.h"
-#include "brw_aub.h"
-#include "brw_util.h"
-#include "program.h"
-#include "imports.h"
-#include "enums.h"
+#include "shader/program.h"
 #include "tnl/tnl.h"
 
+#include "brw_context.h"
+#include "brw_util.h"
 
 static void brwBindProgram( GLcontext *ctx,
 			    GLenum target, 
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index d5175399d6..738ceb0552 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -43,7 +43,7 @@
 #include "brw_sf.h"
 #include "brw_state.h"
 
-#define DO_SETUP_BITS ((1<<FRAG_ATTRIB_MAX)-1)
+#define DO_SETUP_BITS ((1<<(FRAG_ATTRIB_MAX)) - 1)
 
 static void compile_sf_prog( struct brw_context *brw,
 			     struct brw_sf_prog_key *key )
@@ -74,6 +74,11 @@ static void compile_sf_prog( struct brw_context *brw,
       if (c.key.attrs & (1<<i)) {
 	 c.attr_to_idx[i] = idx;
 	 c.idx_to_attr[idx] = i;
+	 if (i >= VERT_RESULT_TEX0 && i <= VERT_RESULT_TEX7) {
+		 c.point_attrs[i].CoordReplace = 
+			brw->attribs.Point->CoordReplace[i - VERT_RESULT_TEX0];
+	 } else
+		 c.point_attrs[i].CoordReplace = GL_FALSE;
 	 idx++;
       }
    
@@ -90,7 +95,10 @@ static void compile_sf_prog( struct brw_context *brw,
       break;
    case SF_POINTS:
       c.nr_verts = 1;
-      brw_emit_point_setup( &c );
+      if (key->do_point_sprite)
+	  brw_emit_point_sprite_setup( &c );
+      else
+	  brw_emit_point_setup( &c );
       break;
    case SF_UNFILLED_TRIS:
       c.nr_verts = 3;
@@ -162,7 +170,8 @@ static void upload_sf_prog( struct brw_context *brw )
       break;
    }
 
-
+   key.do_point_sprite = brw->attribs.Point->PointSprite;
+   key.SpriteOrigin = brw->attribs.Point->SpriteOrigin;
    /* _NEW_LIGHT */
    key.do_flat_shading = (brw->attribs.Light->ShadeModel == GL_FLAT);
    key.do_twoside_color = (brw->attribs.Light->Enabled && brw->attribs.Light->Model.TwoSide);
@@ -179,7 +188,7 @@ static void upload_sf_prog( struct brw_context *brw )
 
 const struct brw_tracked_state brw_sf_prog = {
    .dirty = {
-      .mesa  = (_NEW_LIGHT|_NEW_POLYGON),
+      .mesa  = (_NEW_LIGHT|_NEW_POLYGON|_NEW_POINT),
       .brw   = (BRW_NEW_REDUCED_PRIMITIVE),
       .cache = CACHE_NEW_VS_PROG
    },
diff --git a/src/mesa/drivers/dri/i965/brw_sf.h b/src/mesa/drivers/dri/i965/brw_sf.h
index fb72b84ba8..e8946511dd 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.h
+++ b/src/mesa/drivers/dri/i965/brw_sf.h
@@ -34,9 +34,9 @@
 #define BRW_SF_H
 
 
+#include "shader/program.h"
 #include "brw_context.h"
 #include "brw_eu.h"
-#include "program.h"
 
 
 #define SF_POINTS    0
@@ -50,9 +50,14 @@ struct brw_sf_prog_key {
    GLuint do_flat_shading:1;
    GLuint attrs:16;
    GLuint frontface_ccw:1;
-   GLuint pad:11;
+   GLuint do_point_sprite:1;
+   GLuint pad:10;
+   GLenum SpriteOrigin;
 };
 
+struct brw_sf_point_tex {
+	GLboolean CoordReplace;	
+};
 
 struct brw_sf_compile {
    struct brw_compile func;
@@ -94,12 +99,14 @@ struct brw_sf_compile {
 
    GLubyte attr_to_idx[VERT_RESULT_MAX];   
    GLubyte idx_to_attr[VERT_RESULT_MAX];   
+   struct brw_sf_point_tex point_attrs[VERT_RESULT_MAX];
 };
 
  
 void brw_emit_tri_setup( struct brw_sf_compile *c );
 void brw_emit_line_setup( struct brw_sf_compile *c );
 void brw_emit_point_setup( struct brw_sf_compile *c );
+void brw_emit_point_sprite_setup( struct brw_sf_compile *c );
 void brw_emit_anyprim_setup( struct brw_sf_compile *c );
 
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c
index cbaf018c44..5e86e428fa 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -497,6 +497,86 @@ void brw_emit_line_setup( struct brw_sf_compile *c )
    } 
 }
 
+void brw_emit_point_sprite_setup( struct brw_sf_compile *c )
+{
+   struct brw_compile *p = &c->func;
+   GLuint i;
+
+   c->nr_verts = 1;
+   alloc_regs(c);
+   copy_z_inv_w(c);
+   for (i = 0; i < c->nr_setup_regs; i++)
+   {
+      struct brw_sf_point_tex *tex = &c->point_attrs[c->idx_to_attr[2*i]];
+      struct brw_reg a0 = offset(c->vert[0], i);
+      GLushort pc, pc_persp, pc_linear;
+      GLboolean last = calculate_masks(c, i, &pc, &pc_persp, &pc_linear);
+            
+      if (pc_persp)
+      {				
+	  if (!tex->CoordReplace) {
+	      brw_set_predicate_control_flag_value(p, pc_persp);
+	      brw_MUL(p, a0, a0, c->inv_w[0]);
+	  }
+      }
+
+      if (tex->CoordReplace) {
+	  /* Caculate 1.0/PointWidth */
+	  brw_math(&c->func,
+		  c->tmp,
+		  BRW_MATH_FUNCTION_INV,
+		  BRW_MATH_SATURATE_NONE,
+		  0,
+		  c->dx0,
+		  BRW_MATH_DATA_SCALAR,
+		  BRW_MATH_PRECISION_FULL);
+
+	  if (c->key.SpriteOrigin == GL_UPPER_LEFT) {
+	   	brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
+		brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
+	  	brw_MUL(p, c->m2Cy, c->tmp, negate(c->inv_w[0]));
+		brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
+	  } else {
+	   	brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]);
+		brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0));
+	  	brw_MUL(p, c->m2Cy, c->tmp, c->inv_w[0]);
+		brw_MOV(p, vec1(suboffset(c->m2Cy, 0)), brw_imm_f(0.0));
+	  }
+      } else {
+	  brw_MOV(p, c->m1Cx, brw_imm_ud(0));
+	  brw_MOV(p, c->m2Cy, brw_imm_ud(0));
+      }
+
+      {
+	 brw_set_predicate_control_flag_value(p, pc); 
+	 if (tex->CoordReplace) {
+	     if (c->key.SpriteOrigin == GL_UPPER_LEFT) {
+		 brw_MUL(p, c->m3C0, c->inv_w[0], brw_imm_f(1.0));
+		 brw_MOV(p, vec1(suboffset(c->m3C0, 0)), brw_imm_f(0.0));
+	     }
+	     else
+		 brw_MOV(p, c->m3C0, brw_imm_f(0.0));
+	 } else {
+	 	brw_MOV(p, c->m3C0, a0); /* constant value */
+	 }
+
+	 /* Copy m0..m3 to URB. 
+	  */
+	 brw_urb_WRITE(p, 
+		       brw_null_reg(),
+		       0,
+		       brw_vec8_grf(0, 0),
+		       0, 	/* allocate */
+		       1,	/* used */
+		       4, 	/* msg len */
+		       0,	/* response len */
+		       last, 	/* eot */
+		       last, 	/* writes complete */
+		       i*4,	/* urb destination offset */
+		       BRW_URB_SWIZZLE_TRANSPOSE);
+      }
+   }
+}
 
 /* Points setup - several simplifications as all attributes are
  * constant across the face of the point (point sprites excluded!)
@@ -561,6 +641,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
    struct brw_compile *p = &c->func;
    struct brw_reg ip = brw_ip_reg();
    struct brw_reg payload_prim = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0);
+   struct brw_reg payload_attr = get_element_ud(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), 0); 
    struct brw_reg primmask;
    struct brw_instruction *jmp;
    struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
@@ -582,7 +663,9 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
 					       (1<<_3DPRIM_TRIFAN_NOSTIPPLE)));
    jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
    {
+      brw_push_insn_state(p); 
       brw_emit_tri_setup( c );
+      brw_pop_insn_state(p);
       /* note - thread killed in subroutine */
    }
    brw_land_fwd_jump(p, jmp);
@@ -596,11 +679,23 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
 					       (1<<_3DPRIM_LINESTRIP_CONT_BF)));
    jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
    {
+      brw_push_insn_state(p); 
       brw_emit_line_setup( c );
+      brw_pop_insn_state(p);
       /* note - thread killed in subroutine */
    }
    brw_land_fwd_jump(p, jmp); 
 
+   brw_set_conditionalmod(p, BRW_CONDITIONAL_Z);
+   brw_AND(p, v1_null_ud, payload_attr, brw_imm_ud(1<<BRW_SPRITE_POINT_ENABLE));
+   jmp = brw_JMPI(p, ip, ip, brw_imm_w(0));
+   {
+      brw_push_insn_state(p); 
+      brw_emit_point_sprite_setup( c );
+      brw_pop_insn_state(p);
+   }
+   brw_land_fwd_jump(p, jmp); 
+
    brw_emit_point_setup( c );
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index 9a6e5f5f19..236c6fd42a 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -185,7 +185,9 @@ static void upload_sf_unit( struct brw_context *brw )
    /* _NEW_POINT */
    sf.sf6.point_rast_rule = 1;	/* opengl conventions */
    /* XXX clamp max depends on AA vs. non-AA */
-   sf.sf7.point_size = CLAMP(brw->attribs.Point->Size, 1.0, 3.0) * (1<<3);
+
+   sf.sf7.sprite_point = brw->attribs.Point->PointSprite;
+   sf.sf7.point_size = CLAMP(brw->attribs.Point->Size, 1.0, 255.0) * (1<<3);
    sf.sf7.use_point_size_state = !brw->attribs.Point->_Attenuated;
       
    /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 909b0acd12..b78b51328a 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -32,7 +32,6 @@
 
 
 #include "brw_state.h"
-#include "brw_aub.h"
 #include "intel_batchbuffer.h"
 #include "imports.h"
 
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 71c6938f9a..98d765ac0e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -31,7 +31,6 @@
       
 
 #include "brw_state.h"
-#include "brw_aub.h"
 #include "intel_batchbuffer.h"
 #include "imports.h"
 
@@ -188,13 +187,11 @@ GLuint brw_upload_cache( struct brw_cache *cache,
 
    /* Copy data to the buffer:
     */
-   bmBufferSubDataAUB(&cache->brw->intel,
-		      cache->pool->buffer,
-		      offset, 
-		      data_size, 
-		      data,
-		      cache->aub_type,
-		      cache->aub_sub_type);
+   bmBufferSubData(&cache->brw->intel,
+		   cache->pool->buffer,
+		   offset,
+		   data_size,
+		   data);
    
 
    cache->brw->state.dirty.cache |= 1<<cache->id;
@@ -227,17 +224,17 @@ GLuint brw_cache_data(struct brw_cache *cache,
    return brw_cache_data_sz(cache, data, cache->key_size);
 }
 
-
-
-
+enum pool_type {
+   DW_SURFACE_STATE,
+   DW_GENERAL_STATE
+};
 
 static void brw_init_cache( struct brw_context *brw, 
 			    const char *name,
 			    GLuint id,
 			    GLuint key_size,
 			    GLuint aux_size,
-			    GLuint aub_type,
-			    GLuint aub_sub_type )
+			    enum pool_type pool_type)
 {
    struct brw_cache *cache = &brw->cache[id];
    cache->brw = brw;
@@ -254,9 +251,7 @@ static void brw_init_cache( struct brw_context *brw,
 
    cache->key_size = key_size;
    cache->aux_size = aux_size;
-   cache->aub_type = aub_type;
-   cache->aub_sub_type = aub_sub_type;
-   switch (aub_type) {
+   switch (pool_type) {
    case DW_GENERAL_STATE: cache->pool = &brw->pool[BRW_GS_POOL]; break;
    case DW_SURFACE_STATE: cache->pool = &brw->pool[BRW_SS_POOL]; break;
    default: assert(0); break;
@@ -271,136 +266,119 @@ void brw_init_caches( struct brw_context *brw )
 		  BRW_CC_VP,
 		  sizeof(struct brw_cc_viewport),
 		  0,
-		  DW_GENERAL_STATE,
-		  DWGS_COLOR_CALC_VIEWPORT_STATE);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "CC_UNIT",
 		  BRW_CC_UNIT,
 		  sizeof(struct brw_cc_unit_state),
 		  0,
-		  DW_GENERAL_STATE,
-		  DWGS_COLOR_CALC_STATE);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "WM_PROG",
 		  BRW_WM_PROG,
 		  sizeof(struct brw_wm_prog_key),
 		  sizeof(struct brw_wm_prog_data),
-		  DW_GENERAL_STATE,
-		  DWGS_KERNEL_INSTRUCTIONS);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "SAMPLER_DEFAULT_COLOR",
 		  BRW_SAMPLER_DEFAULT_COLOR,
 		  sizeof(struct brw_sampler_default_color),
 		  0,
-		  DW_GENERAL_STATE,
-		  DWGS_SAMPLER_DEFAULT_COLOR);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "SAMPLER",
 		  BRW_SAMPLER,
 		  0,		/* variable key/data size */
 		  0,
-		  DW_GENERAL_STATE,
-		  DWGS_SAMPLER_STATE);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "WM_UNIT",
 		  BRW_WM_UNIT,
 		  sizeof(struct brw_wm_unit_state),
 		  0,
-		  DW_GENERAL_STATE,
-		  DWGS_WINDOWER_IZ_STATE);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "SF_PROG",
 		  BRW_SF_PROG,
 		  sizeof(struct brw_sf_prog_key),
 		  sizeof(struct brw_sf_prog_data),
-		  DW_GENERAL_STATE,
-		  DWGS_KERNEL_INSTRUCTIONS);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "SF_VP",
 		  BRW_SF_VP,
 		  sizeof(struct brw_sf_viewport),
 		  0,
-		  DW_GENERAL_STATE,
-		  DWGS_STRIPS_FANS_VIEWPORT_STATE);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "SF_UNIT",
 		  BRW_SF_UNIT,
 		  sizeof(struct brw_sf_unit_state),
 		  0,
-		  DW_GENERAL_STATE,
-		  DWGS_STRIPS_FANS_STATE);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "VS_UNIT",
 		  BRW_VS_UNIT,
 		  sizeof(struct brw_vs_unit_state),
 		  0,
-		  DW_GENERAL_STATE,
-		  DWGS_VERTEX_SHADER_STATE);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "VS_PROG",
 		  BRW_VS_PROG,
 		  sizeof(struct brw_vs_prog_key),
 		  sizeof(struct brw_vs_prog_data),
-		  DW_GENERAL_STATE,
-		  DWGS_KERNEL_INSTRUCTIONS);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "CLIP_UNIT",
 		  BRW_CLIP_UNIT,
 		  sizeof(struct brw_clip_unit_state),
 		  0,
-		  DW_GENERAL_STATE,
-		  DWGS_CLIPPER_STATE);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "CLIP_PROG",
 		  BRW_CLIP_PROG,
 		  sizeof(struct brw_clip_prog_key),
 		  sizeof(struct brw_clip_prog_data),
-		  DW_GENERAL_STATE,
-		  DWGS_KERNEL_INSTRUCTIONS);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "GS_UNIT",
 		  BRW_GS_UNIT,
 		  sizeof(struct brw_gs_unit_state),
 		  0,
-		  DW_GENERAL_STATE,
-		  DWGS_GEOMETRY_SHADER_STATE);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "GS_PROG",
 		  BRW_GS_PROG,
 		  sizeof(struct brw_gs_prog_key),
 		  sizeof(struct brw_gs_prog_data),
-		  DW_GENERAL_STATE,
-		  DWGS_KERNEL_INSTRUCTIONS);
+		  DW_GENERAL_STATE);
 
    brw_init_cache(brw,
 		  "SS_SURFACE",
 		  BRW_SS_SURFACE,
 		  sizeof(struct brw_surface_state),
 		  0,
-		  DW_SURFACE_STATE,
-		  DWSS_SURFACE_STATE);
+		  DW_SURFACE_STATE);
 
    brw_init_cache(brw,
 		  "SS_SURF_BIND",
 		  BRW_SS_SURF_BIND,
 		  sizeof(struct brw_surface_binding_table),
 		  0,
-		  DW_SURFACE_STATE,
-		  DWSS_BINDING_TABLE_STATE);
+		  DW_SURFACE_STATE);
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_state_pool.c b/src/mesa/drivers/dri/i965/brw_state_pool.c
index b9926f2a5d..708ae857ab 100644
--- a/src/mesa/drivers/dri/i965/brw_state_pool.c
+++ b/src/mesa/drivers/dri/i965/brw_state_pool.c
@@ -126,10 +126,7 @@ void brw_pool_check_wrap( struct brw_context *brw,
 			  struct brw_mem_pool *pool )
 {
    if (pool->offset > (pool->size * 3) / 4) {
-      if (brw->intel.aub_file)
-	 brw->intel.aub_wrap = 1;
-      else
-	 brw->state.dirty.brw |= BRW_NEW_CONTEXT;
+      brw->state.dirty.brw |= BRW_NEW_CONTEXT;
    }
 
 }
diff --git a/src/mesa/drivers/dri/i965/brw_tex.c b/src/mesa/drivers/dri/i965/brw_tex.c
index 9d4b9867d2..ad29316a42 100644
--- a/src/mesa/drivers/dri/i965/brw_tex.c
+++ b/src/mesa/drivers/dri/i965/brw_tex.c
@@ -154,13 +154,19 @@ brwChooseTextureFormat( GLcontext *ctx, GLint internalFormat,
 
    case GL_RGB_S3TC:
    case GL_RGB4_S3TC:
+   case GL_COMPRESSED_RGB_S3TC_DXT1_EXT:
+       return &_mesa_texformat_rgb_dxt1;
+
+   case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT:
+       return &_mesa_texformat_rgba_dxt1;
+
    case GL_RGBA_S3TC:
    case GL_RGBA4_S3TC:
    case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT:
+       return &_mesa_texformat_rgba_dxt3;
+
    case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT:
-   case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT:
-   case GL_COMPRESSED_RGB_S3TC_DXT1_EXT:
-     return &_mesa_texformat_rgb_dxt1; /* there is no rgba support? */
+       return &_mesa_texformat_rgba_dxt5;
 
    case GL_DEPTH_COMPONENT:
    case GL_DEPTH_COMPONENT16:
@@ -168,6 +174,25 @@ brwChooseTextureFormat( GLcontext *ctx, GLint internalFormat,
    case GL_DEPTH_COMPONENT32:
       return &_mesa_texformat_z16;
 
+   case GL_SRGB_EXT:
+   case GL_SRGB8_EXT:
+   case GL_SRGB_ALPHA_EXT:
+   case GL_SRGB8_ALPHA8_EXT:
+   case GL_SLUMINANCE_EXT:
+   case GL_SLUMINANCE8_EXT:
+   case GL_SLUMINANCE_ALPHA_EXT:
+   case GL_SLUMINANCE8_ALPHA8_EXT:
+   case GL_COMPRESSED_SRGB_EXT:
+   case GL_COMPRESSED_SRGB_ALPHA_EXT:
+   case GL_COMPRESSED_SLUMINANCE_EXT:
+   case GL_COMPRESSED_SLUMINANCE_ALPHA_EXT:
+	return &_mesa_texformat_srgba8;
+   case GL_COMPRESSED_SRGB_S3TC_DXT1_EXT:
+   case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT:
+   case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT:
+   case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT:
+     return &_mesa_texformat_srgb_dxt1;
+
    default:
       fprintf(stderr, "unexpected texture format %s in %s\n", 
 	      _mesa_lookup_enum_by_nr(internalFormat),
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index af1ad0f1ef..2094a1c8ad 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -37,6 +37,7 @@
 #include "intel_tex_layout.h"
 #include "macros.h"
 
+#define ALIGN(value, alignment)  ((value + alignment - 1) & ~(alignment - 1))
 
 GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt )
 {
@@ -53,11 +54,20 @@ GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt )
       GLuint pack_x_pitch, pack_x_nr;
       GLuint pack_y_pitch;
       GLuint level;
+      GLuint align_h = 2;
+      GLuint align_w = 4;
 
-      mt->pitch = ((mt->width0 * mt->cpp + 3) & ~3) / mt->cpp;
       mt->total_height = 0;
+      
+      if (mt->compressed) {
+          align_w = intel_compressed_alignment(mt->internal_format);
+          mt->pitch = ALIGN(width, align_w);
+          pack_y_pitch = (height + 3) / 4;
+      } else {
+          mt->pitch = ((mt->width0 * mt->cpp + 3) & ~3) / mt->cpp;
+          pack_y_pitch = ALIGN(mt->height0, align_h);
+      }
 
-      pack_y_pitch = MAX2(mt->height0, 2);
       pack_x_pitch = mt->pitch;
       pack_x_nr = 1;
 
@@ -83,20 +93,30 @@ GLboolean brw_miptree_layout( struct intel_mipmap_tree *mt )
 
 
 	 mt->total_height += y;
-
-	 if (pack_x_pitch > 4) {
-	    pack_x_pitch >>= 1;
-	    pack_x_nr <<= 1;
-	    assert(pack_x_pitch * pack_x_nr <= mt->pitch);
-	 }
-
-	 if (pack_y_pitch > 2) {
-	    pack_y_pitch >>= 1;
-	 }
-
 	 width  = minify(width);
 	 height = minify(height);
 	 depth  = minify(depth);
+
+    if (mt->compressed) {
+        pack_y_pitch = (height + 3) / 4;
+        
+        if (pack_x_pitch > ALIGN(width, align_w)) {
+            pack_x_pitch = ALIGN(width, align_w);
+            pack_x_nr <<= 1;
+        }
+    } else {
+        if (pack_x_pitch > 4) {
+            pack_x_pitch >>= 1;
+            pack_x_nr <<= 1;
+            assert(pack_x_pitch * pack_x_nr <= mt->pitch);
+        }
+
+        if (pack_y_pitch > 2) {
+            pack_y_pitch >>= 1;
+            pack_y_pitch = ALIGN(pack_y_pitch, align_h);
+        }
+    }
+
       }
       break;
    }
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h b/src/mesa/drivers/dri/i965/brw_vs.h
index fdb5785d67..8843f816f9 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.h
+++ b/src/mesa/drivers/dri/i965/brw_vs.h
@@ -36,7 +36,7 @@
 
 #include "brw_context.h"
 #include "brw_eu.h"
-#include "program.h"
+#include "shader/program.h"
 
 
 struct brw_vs_prog_key {
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 6eb11b19ad..8733b470c2 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -30,8 +30,8 @@
   */
             
 
-#include "program.h"
-#include "macros.h"
+#include "main/macros.h"
+#include "shader/program.h"
 #include "shader/prog_parameter.h"
 #include "shader/prog_print.h"
 #include "brw_context.h"
@@ -201,7 +201,7 @@ static void unalias2( struct brw_vs_compile *c,
 				    struct brw_reg,
 				    struct brw_reg ))
 {
-   if ((dst.file == arg0.file && dst.nr == arg0.nr) &&
+   if ((dst.file == arg0.file && dst.nr == arg0.nr) ||
        (dst.file == arg1.file && dst.nr == arg1.nr)) {
       struct brw_compile *p = &c->func;
       struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask);
diff --git a/src/mesa/drivers/dri/i965/brw_vs_tnl.c b/src/mesa/drivers/dri/i965/brw_vs_tnl.c
index b69be350a9..27210d1a37 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_tnl.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_tnl.c
@@ -1000,13 +1000,19 @@ static void build_lighting( struct tnl_program *p )
 					       STATE_POSITION); 
 	    struct ureg V = get_eye_position(p);
 	    struct ureg dist = get_temp(p);
+       struct ureg tmpPpli = get_temp(p);
 
 	    VPpli = get_temp(p); 
 	    half = get_temp(p);
+
+       /* In homogeneous object coordinates
+        */
+       emit_op1(p, OPCODE_RCP, dist, 0, swizzle1(Ppli, W));
+       emit_op2(p, OPCODE_MUL, tmpPpli, 0, Ppli, dist);
  
 	    /* Calulate VPpli vector
 	     */
-	    emit_op2(p, OPCODE_SUB, VPpli, 0, Ppli, V); 
+	    emit_op2(p, OPCODE_SUB, VPpli, 0, tmpPpli, V); 
 
 	    /* Normalize VPpli.  The dist value also used in
 	     * attenuation below.
@@ -1038,6 +1044,7 @@ static void build_lighting( struct tnl_program *p )
 	    emit_normalize_vec3(p, half, half);
 
 	    release_temp(p, dist);
+       release_temp(p, tmpPpli);
 	 }
 
 	 /* Calculate dot products:
@@ -1621,7 +1628,8 @@ const struct brw_tracked_state brw_tnl_vertprog = {
 	       _NEW_FOG | 
 	       _NEW_HINT | 
 	       _NEW_POINT | 
-	       _NEW_TEXTURE),
+	       _NEW_TEXTURE |
+          _NEW_TEXTURE_MATRIX),
       .brw = (BRW_NEW_FRAGMENT_PROGRAM | 
 	      BRW_NEW_INPUT_VARYING),
       .cache = 0
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 786f30e641..d8cb168802 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -47,7 +47,6 @@
 
 #include "brw_draw.h"
 #include "brw_state.h"
-#include "brw_aub.h"
 #include "brw_fallback.h"
 #include "brw_vs.h"
 
@@ -60,8 +59,6 @@ static void brw_destroy_context( struct intel_context *intel )
    GLcontext *ctx = &intel->ctx;
    struct brw_context *brw = brw_context(&intel->ctx);
 
-   brw_aub_destroy(brw);
-
    brw_destroy_metaops(brw);
    brw_destroy_state(brw);
    brw_draw_destroy( brw );
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 1497dc7968..904c00bef8 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -285,7 +285,7 @@ static void brw_wm_populate_key( struct brw_context *brw,
 
 
    /* BRW_NEW_WM_INPUT_DIMENSIONS */
-   key->projtex_mask = brw->wm.input_size_masks[4-1]; 
+   key->projtex_mask = brw->wm.input_size_masks[4-1] >> (FRAG_ATTRIB_TEX0 - FRAG_ATTRIB_WPOS); 
 
    /* _NEW_LIGHT */
    key->flat_shade = (brw->attribs.Light->ShadeModel == GL_FLAT);
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index f5fddfdb68..6dcf4732a9 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -34,9 +34,9 @@
 #define BRW_WM_H
 
 
+#include "shader/prog_instruction.h"
 #include "brw_context.h"
 #include "brw_eu.h"
-#include "prog_instruction.h"
 
 /* A big lookup table is used to figure out which and how many
  * additional regs will inserted before the main payload in the WM
diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c
index ff97d87dc4..67154c1b13 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_fp.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c
@@ -525,7 +525,57 @@ static void precalc_tex( struct brw_wm_compile *c,
    struct prog_src_register coord;
    struct prog_dst_register tmpcoord;
 
-   if (inst->TexSrcTarget == TEXTURE_RECT_INDEX) {
+   if (inst->TexSrcTarget == TEXTURE_CUBE_INDEX) {
+       struct prog_instruction *out;
+       struct prog_dst_register tmp0 = get_temp(c);
+       struct prog_src_register tmp0src = src_reg_from_dst(tmp0);
+       struct prog_dst_register tmp1 = get_temp(c);
+       struct prog_src_register tmp1src = src_reg_from_dst(tmp1);
+       struct prog_src_register src0 = inst->SrcReg[0];
+
+       tmpcoord = get_temp(c);
+       coord = src_reg_from_dst(tmpcoord);
+
+       out = emit_op(c, OPCODE_MOV,
+                     tmpcoord,
+                     0, 0, 0,
+                     src0,
+                     src_undef(),
+                     src_undef());
+       out->SrcReg[0].NegateBase = 0;
+       out->SrcReg[0].Abs = 1;
+
+       emit_op(c, OPCODE_MAX,
+               tmp0,
+               0, 0, 0,
+               src_swizzle1(coord, X),
+               src_swizzle1(coord, Y),
+               src_undef());
+
+       emit_op(c, OPCODE_MAX,
+               tmp1,
+               0, 0, 0,
+               tmp0src,
+               src_swizzle1(coord, Z),
+               src_undef());
+
+       emit_op(c, OPCODE_RCP,
+               tmp0,
+               0, 0, 0,
+               tmp1src,
+               src_undef(),
+               src_undef());
+
+       emit_op(c, OPCODE_MUL,
+               tmpcoord,
+               0, 0, 0,
+               src0,
+               tmp0src,
+               src_undef());
+
+       release_temp(c, tmp0);
+       release_temp(c, tmp1);
+   } else if (inst->TexSrcTarget == TEXTURE_RECT_INDEX) {
       struct prog_src_register scale = 
 	 search_or_add_param5( c, 
 			       STATE_INTERNAL, 
@@ -660,7 +710,7 @@ static GLboolean projtex( struct brw_wm_compile *c,
       return 0;  /* ut2004 gun rendering !?! */
    else if (src.File == PROGRAM_INPUT && 
 	    GET_SWZ(src.Swizzle, W) == W &&
-	    (c->key.projtex_mask & (1<<src.Index)) == 0)
+           (c->key.projtex_mask & (1<<(src.Index + FRAG_ATTRIB_WPOS - FRAG_ATTRIB_TEX0))) == 0)
       return 0;
    else
       return 1;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 93d4cfc3a5..3c0952acf0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -54,7 +54,7 @@ static GLuint translate_wrap_mode( GLenum wrap )
    case GL_REPEAT: 
       return BRW_TEXCOORDMODE_WRAP;
    case GL_CLAMP:  
-      return BRW_TEXCOORDMODE_CLAMP_BORDER; /* conform likes it this way */
+      return BRW_TEXCOORDMODE_CLAMP;
    case GL_CLAMP_TO_EDGE: 
       return BRW_TEXCOORDMODE_CLAMP; /* conform likes it this way */
    case GL_CLAMP_TO_BORDER: 
@@ -173,12 +173,12 @@ static void brw_update_sampler_state( struct gl_texture_unit *texUnit,
        * message (sample_c).  So need to recompile WM program when
        * shadow comparison is enabled on each/any texture unit.
        */
-      sampler->ss0.shadow_function = intel_translate_compare_func(texObj->CompareFunc);
+      sampler->ss0.shadow_function = intel_translate_shadow_compare_func(texObj->CompareFunc);
    }
 
    /* Set LOD bias: 
     */
-   sampler->ss0.lod_bias = S_FIXED(texUnit->LodBias + texObj->LodBias, 6);
+   sampler->ss0.lod_bias = S_FIXED(CLAMP(texUnit->LodBias + texObj->LodBias, -16, 15), 6);
 
    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
@@ -192,8 +192,8 @@ static void brw_update_sampler_state( struct gl_texture_unit *texUnit,
     */
    sampler->ss0.base_level = U_FIXED(0, 1);
 
-   sampler->ss1.max_lod = U_FIXED(MAX2(texObj->MaxLod, 0), 6);
-   sampler->ss1.min_lod = U_FIXED(MAX2(texObj->MinLod, 0), 6);
+   sampler->ss1.max_lod = U_FIXED(MIN2(MAX2(texObj->MaxLod, 0), 13), 6);
+   sampler->ss1.min_lod = U_FIXED(MIN2(MAX2(texObj->MinLod, 0), 13), 6);
    
    sampler->ss2.default_color_pointer = sdc_gs_offset >> 5;
 }
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index ff5cb31bdd..5b4f2abd0e 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -117,7 +117,7 @@ static void upload_wm_unit(struct brw_context *brw )
    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 
    /* CACHE_NEW_SAMPLER */
-   wm.wm4.sampler_count = brw->wm.sampler_count;
+   wm.wm4.sampler_count = (brw->wm.sampler_count + 1) / 4;
    wm.wm4.sampler_state_pointer = brw->wm.sampler_gs_offset >> 5;
 
    /* BRW_NEW_FRAGMENT_PROGRAM */
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d24c618a66..0a45164a0f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -114,11 +114,24 @@ static GLuint translate_tex_format( GLuint mesa_format )
       return BRW_SURFACEFORMAT_FXT1;
 
    case MESA_FORMAT_Z16:
-      return BRW_SURFACEFORMAT_L16_UNORM;
+      return BRW_SURFACEFORMAT_I16_UNORM;
 
-   case MESA_FORMAT_RGBA_DXT1:
    case MESA_FORMAT_RGB_DXT1:
-      return BRW_SURFACEFORMAT_DXT1_RGB;
+       return BRW_SURFACEFORMAT_DXT1_RGB;
+
+   case MESA_FORMAT_RGBA_DXT1:
+       return BRW_SURFACEFORMAT_BC1_UNORM;
+       
+   case MESA_FORMAT_RGBA_DXT3:
+       return BRW_SURFACEFORMAT_BC2_UNORM;
+       
+   case MESA_FORMAT_RGBA_DXT5:
+       return BRW_SURFACEFORMAT_BC3_UNORM;
+
+   case MESA_FORMAT_SRGBA8:
+      return BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB;
+   case MESA_FORMAT_SRGB_DXT1:
+      return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 
    default:
       assert(0);
diff --git a/src/mesa/drivers/dri/i965/bufmgr.h b/src/mesa/drivers/dri/i965/bufmgr.h
index e748c0d6d0..b31c2e6d9b 100644
--- a/src/mesa/drivers/dri/i965/bufmgr.h
+++ b/src/mesa/drivers/dri/i965/bufmgr.h
@@ -130,24 +130,6 @@ int bmBufferSubData(struct intel_context *,
 		     unsigned size, 
 		     const void *data );
 
-
-int bmBufferDataAUB(struct intel_context *, 
-		     struct buffer *buf, 
-		     unsigned size, 
-		     const void *data, 
-		     unsigned flags,
-		     unsigned aubtype,
-		     unsigned aubsubtype );
-
-int bmBufferSubDataAUB(struct intel_context *, 
-			struct buffer *buf, 
-			unsigned offset, 
-			unsigned size, 
-			const void *data,
-			unsigned aubtype,
-			unsigned aubsubtype );
-
-
 /* In this version, taking the offset will provoke an upload on
  * buffers not already resident in AGP:
  */
@@ -170,12 +152,6 @@ void *bmMapBuffer( struct intel_context *,
 void bmUnmapBuffer( struct intel_context *,
 		    struct buffer *buf );
 
-void bmUnmapBufferAUB( struct intel_context *,
-		       struct buffer *buf,
-		       unsigned aubtype,
-		       unsigned aubsubtype );
-
-
 /* Pertains to all buffers who's offset has been taken since the last
  * fence or release.
  */
diff --git a/src/mesa/drivers/dri/i965/bufmgr_fake.c b/src/mesa/drivers/dri/i965/bufmgr_fake.c
index 24ee11edd8..a85121122f 100644
--- a/src/mesa/drivers/dri/i965/bufmgr_fake.c
+++ b/src/mesa/drivers/dri/i965/bufmgr_fake.c
@@ -85,7 +85,6 @@ struct buffer {
 
    unsigned mapped:1;		
    unsigned dirty:1;		
-   unsigned aub_dirty:1;	
    unsigned alignment:13;
    unsigned flags:16;
 
@@ -906,86 +905,6 @@ int bmBufferSubData(struct intel_context *intel,
    return retval;
 }
 
-
-
-int bmBufferDataAUB(struct intel_context *intel, 
-		     struct buffer *buf, 
-		     unsigned size, 
-		     const void *data, 
-		     unsigned flags,
-		     unsigned aubtype,
-		     unsigned aubsubtype )
-{
-   int retval = bmBufferData(intel, buf, size, data, flags);
-   
-
-   /* This only works because in this version of the buffer manager we
-    * allocate all buffers statically in agp space and so can emit the
-    * uploads to the aub file with the correct offsets as they happen.
-    */
-   if (retval == 0 && data && intel->aub_file) {
-
-      if (buf->block && !buf->dirty) {
-	 intel->vtbl.aub_gtt_data(intel,
-				      buf->block->mem->ofs,
-				      buf->block->virtual,
-				      size,
-				      aubtype,
-				      aubsubtype);
-	 buf->aub_dirty = 0;
-      }
-   }
-   
-   return retval;
-}
-		       
-
-int bmBufferSubDataAUB(struct intel_context *intel, 
-			struct buffer *buf, 
-			unsigned offset, 
-			unsigned size, 
-			const void *data,
-			unsigned aubtype,
-			unsigned aubsubtype )
-{
-   int retval = bmBufferSubData(intel, buf, offset, size, data);
-   
-
-   /* This only works because in this version of the buffer manager we
-    * allocate all buffers statically in agp space and so can emit the
-    * uploads to the aub file with the correct offsets as they happen.
-    */
-   if (intel->aub_file) {
-      if (retval == 0 && buf->block && !buf->dirty)
-	 intel->vtbl.aub_gtt_data(intel,
-				      buf->block->mem->ofs + offset,
-				      ((const char *)buf->block->virtual) + offset,
-				      size,
-				      aubtype,
-				      aubsubtype);
-   }
-
-   return retval;
-}
-
-void bmUnmapBufferAUB( struct intel_context *intel, 
-		       struct buffer *buf,
-		       unsigned aubtype,
-		       unsigned aubsubtype )
-{
-   bmUnmapBuffer(intel, buf);
-
-   if (intel->aub_file) {
-      /* Hack - exclude the framebuffer mappings.  If you removed
-       * this, you'd get very big aubfiles, but you *would* be able to
-       * see fallback rendering.
-       */
-      if (buf->block  && !buf->dirty && buf->block->pool == &intel->bm->pool[0]) {
-	 buf->aub_dirty = 1;
-      }
-   }
-}
-
 unsigned bmBufferOffset(struct intel_context *intel, 
 			struct buffer *buf)
 {
@@ -1197,26 +1116,7 @@ int bmValidateBuffers( struct intel_context *intel )
 			 buf->backing_store, 
 			 buf->size);
 
-	       if (intel->aub_file) {
-		  intel->vtbl.aub_gtt_data(intel,
-					       buf->block->mem->ofs,
-					       buf->backing_store,
-					       buf->size,
-					       0,
-					       0);
-	       }
-
 	       buf->dirty = 0;
-	       buf->aub_dirty = 0;
-	    }
-	    else if (buf->aub_dirty) {
-	       intel->vtbl.aub_gtt_data(intel,
-					    buf->block->mem->ofs,
-					    buf->block->virtual,
-					    buf->size,
-					    0,
-					    0);
-	       buf->aub_dirty = 0;
 	    }
 
 	    block->referenced = 0;
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 64885ed9b4..fb58c0e708 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -28,6 +28,7 @@
 #include "imports.h"
 #include "intel_batchbuffer.h"
 #include "intel_ioctl.h"
+#include "intel_decode.h"
 #include "bufmgr.h"
 
 
@@ -168,31 +169,22 @@ GLboolean intel_batchbuffer_flush( struct intel_batchbuffer *batch )
       goto out;
    }
 
+   if (INTEL_DEBUG & DEBUG_BATCH) {
+      char *map;
 
-   if (intel->aub_file) {
-      /* Send buffered commands to aubfile as a single packet. 
-       */
-      intel_batchbuffer_map(batch);
-      ((int *)batch->ptr)[-1] = intel->vtbl.flush_cmd();
-      intel->vtbl.aub_commands(intel,
-			       offset, /* Fulsim wierdness - don't adjust */
-			       batch->map + batch->offset,
-			       used);
-      ((int *)batch->ptr)[-1] = MI_BATCH_BUFFER_END;
-      intel_batchbuffer_unmap(batch);
+      map = bmMapBuffer(batch->intel, batch->buffer,
+			BM_MEM_AGP|BM_MEM_LOCAL|BM_CLIENT);
+      intel_decode((uint32_t *)(map + batch->offset), used / 4,
+		   offset + batch->offset, intel->intelScreen->deviceID);
+      bmUnmapBuffer(batch->intel, batch->buffer);
    }
 
-
    /* Fire the batch buffer, which was uploaded above:
     */
    intel_batch_ioctl(batch->intel, 
 		     offset + batch->offset,
 		     used);
 
-   if (intel->aub_file && 
-       intel->ctx.DrawBuffer->_ColorDrawBufferMask[0] == BUFFER_BIT_FRONT_LEFT)
-      intel->vtbl.aub_dump_bmp( intel, 0 );
-
    /* Reset the buffer:
     */
  out:
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index 015e433fd7..3349284f5d 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -103,8 +103,7 @@ static void intel_bufferobj_data( GLcontext *ctx,
    obj->Size = size;
    obj->Usage = usage;
 
-   bmBufferDataAUB(intel, intel_obj->buffer, size, data, 0,
-		   0, 0);
+   bmBufferData(intel, intel_obj->buffer, size, data, 0);
 }
 
 
@@ -125,7 +124,7 @@ static void intel_bufferobj_subdata( GLcontext *ctx,
    struct intel_buffer_object *intel_obj = intel_buffer_object(obj);
 
    assert(intel_obj);
-   bmBufferSubDataAUB(intel, intel_obj->buffer, offset, size, data, 0, 0);
+   bmBufferSubData(intel, intel_obj->buffer, offset, size, data);
 }
 
 
@@ -181,7 +180,7 @@ static GLboolean intel_bufferobj_unmap( GLcontext *ctx,
    assert(intel_obj);
    assert(intel_obj->buffer);
    assert(obj->Pointer);
-   bmUnmapBufferAUB(intel, intel_obj->buffer, 0, 0);
+   bmUnmapBuffer(intel, intel_obj->buffer);
    obj->Pointer = NULL;
    return GL_TRUE;
 }
diff --git a/src/mesa/drivers/dri/i965/intel_buffers.c b/src/mesa/drivers/dri/i965/intel_buffers.c
index d155c039d7..6c8b073502 100644
--- a/src/mesa/drivers/dri/i965/intel_buffers.c
+++ b/src/mesa/drivers/dri/i965/intel_buffers.c
@@ -450,12 +450,6 @@ void intelSwapBuffers( __DRIdrawablePrivate *dPriv )
 	 } else {
 	    intelCopyBuffer( dPriv, NULL );
 	 }
-	 if (intel->aub_file) {
-	    intelFlush(ctx);
-	    intel->vtbl.aub_dump_bmp( intel, 1 );
-
-	    intel->aub_wrap = 1;
-	 }
       }
    } else {
       /* XXX this shouldn't be an error but we can't handle it for now */
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 4f51fefe0f..2cf311c713 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -46,6 +46,7 @@
 #include "drivers/common/driverfuncs.h"
 
 #include "intel_screen.h"
+#include "intel_chipset.h"
 
 #include "i830_dri.h"
 #include "i830_common.h"
@@ -66,6 +67,7 @@
 int INTEL_DEBUG = (0);
 #endif
 
+#define need_GL_NV_point_sprite
 #define need_GL_ARB_multisample
 #define need_GL_ARB_point_parameters
 #define need_GL_ARB_texture_compression
@@ -81,6 +83,7 @@ int INTEL_DEBUG = (0);
 #define need_GL_EXT_fog_coord
 #define need_GL_EXT_multi_draw_arrays
 #define need_GL_EXT_secondary_color
+#define need_GL_EXT_point_parameters
 #include "extension_helper.h"
 
 #ifndef VERBOSE
@@ -146,6 +149,7 @@ const struct dri_extension card_extensions[] =
     { "GL_ARB_multisample",                GL_ARB_multisample_functions },
     { "GL_ARB_multitexture",               NULL },
     { "GL_ARB_point_parameters",           GL_ARB_point_parameters_functions },
+    { "GL_NV_point_sprite",                GL_NV_point_sprite_functions },
     { "GL_ARB_texture_border_clamp",       NULL },
     { "GL_ARB_texture_compression",        GL_ARB_texture_compression_functions },
     { "GL_ARB_texture_cube_map",           NULL },
@@ -158,6 +162,8 @@ const struct dri_extension card_extensions[] =
     { "GL_NV_texture_rectangle",           NULL },
     { "GL_EXT_texture_rectangle",          NULL },
     { "GL_ARB_texture_rectangle",          NULL },
+    { "GL_ARB_point_sprite",               NULL},
+    { "GL_ARB_point_parameters",	   NULL }, 
     { "GL_ARB_vertex_buffer_object",       GL_ARB_vertex_buffer_object_functions },
     { "GL_ARB_vertex_program",             GL_ARB_vertex_program_functions },
     { "GL_ARB_window_pos",                 GL_ARB_window_pos_functions },
@@ -177,6 +183,7 @@ const struct dri_extension card_extensions[] =
     { "GL_EXT_texture_env_dot3",           NULL },
     { "GL_EXT_texture_filter_anisotropic", NULL },
     { "GL_EXT_texture_lod_bias",           NULL },
+    { "GL_EXT_texture_sRGB",               NULL },
     { "GL_3DFX_texture_compression_FXT1",  NULL },
     { "GL_APPLE_client_storage",           NULL },
     { "GL_MESA_pack_invert",               NULL },
@@ -219,6 +226,7 @@ static const struct dri_debug_control debug_control[] =
     { "thre",  DEBUG_SINGLE_THREAD },
     { "wm",    DEBUG_WM },
     { "vs",    DEBUG_VS },
+    { "bat",   DEBUG_BATCH },
     { NULL,    0 }
 };
 
@@ -265,7 +273,7 @@ intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
 	};
 	intel->stats_wm++;
 	intelFinish(&intel->ctx);
-	drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+	drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
 }
 
 static void
@@ -279,7 +287,7 @@ intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
 		.data = &tmp
 	};
 	intelFinish(&intel->ctx);
-	drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+	drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
 	q->Result = tmp - q->Result;
 	q->Ready = GL_TRUE;
 	intel->stats_wm--;
@@ -570,6 +578,10 @@ GLboolean intelMakeCurrent(__DRIcontextPrivate *driContextPriv,
    if (driContextPriv) {
       struct intel_context *intel = (struct intel_context *) driContextPriv->driverPrivate;
 
+      if (intel->driReadDrawable != driReadPriv) {
+          intel->driReadDrawable = driReadPriv;
+      }
+
       if ( intel->driDrawable != driDrawPriv ) {
 	 /* Shouldn't the readbuffer be stored also? */
 	 driDrawableInitVBlank( driDrawPriv, intel->vblank_flags,
@@ -658,19 +670,12 @@ void LOCK_HARDWARE( struct intel_context *intel )
 
    intel->locked = 1;
 
-   if (intel->aub_wrap) {
-      bm_fake_NotifyContendedLockTake( intel ); 
-      intel->vtbl.lost_hardware( intel );
-      intel->vtbl.aub_wrap(intel);
-      intel->aub_wrap = 0;
-   }
-
    if (bmError(intel)) {
       bmEvictAll(intel);
       intel->vtbl.lost_hardware( intel );
    }
 
-   /* Make sure nothing has been emitted prior to getting the lock: 
+   /* Make sure nothing has been emitted prior to getting the lock:
     */
    assert(intel->batch->map == 0);
 
@@ -703,8 +708,6 @@ void UNLOCK_HARDWARE( struct intel_context *intel )
    intel->vtbl.note_unlock( intel );
    intel->locked = 0;
 
-
-
    DRM_UNLOCK(intel->driFd, intel->driHwLock, intel->hHWContext);
    _glthread_UNLOCK_MUTEX(lockMutex); 
 }
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 406f8483dc..f63c2f613d 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -109,20 +109,6 @@ struct intel_context
       void (*emit_flush)( struct intel_context *intel,
 			  GLuint unused );
 
-      void (*aub_commands)( struct intel_context *intel, 
-			    GLuint offset,
-			    const void *buf,
-			    GLuint sz );
-      void (*aub_dump_bmp)( struct intel_context *intel, GLuint buffer );
-      void (*aub_wrap)( struct intel_context *intel );
-      void (*aub_gtt_data)( struct intel_context *intel, 
-			    GLuint offset,
-			    const void *src,
-			    GLuint size,
-			    GLuint aubtype, 
-			    GLuint aubsubtype);
-
-
       void (*reduced_primitive_state)( struct intel_context *intel, GLenum rprim );
 
       GLboolean (*check_vertex_size)( struct intel_context *intel, GLuint expected );
@@ -176,7 +162,6 @@ struct intel_context
    GLuint last_swap_fence;
    GLuint second_last_swap_fence;
    
-   GLboolean aub_wrap;
    GLuint stats_wm;
 
    struct intel_batchbuffer *batch;
@@ -234,11 +219,10 @@ struct intel_context
    int driFd;
 
    __DRIdrawablePrivate *driDrawable;
+   __DRIdrawablePrivate *driReadDrawable;
    __DRIscreenPrivate *driScreen;
    intelScreenPrivate *intelScreen; 
    volatile drmI830Sarea *sarea; 
-   
-   FILE *aub_file;
 
    GLuint lastStamp;
 
@@ -371,22 +355,7 @@ extern int INTEL_DEBUG;
 #define DEBUG_WM        0x10000
 #define DEBUG_URB       0x20000
 #define DEBUG_VS        0x40000
-
-
-#define PCI_CHIP_845_G			0x2562
-#define PCI_CHIP_I830_M			0x3577
-#define PCI_CHIP_I855_GM		0x3582
-#define PCI_CHIP_I865_G			0x2572
-#define PCI_CHIP_I915_G			0x2582
-#define PCI_CHIP_I915_GM		0x2592
-#define PCI_CHIP_I945_G			0x2772
-#define PCI_CHIP_I965_G			0x29A2
-#define PCI_CHIP_I965_Q			0x2992
-#define PCI_CHIP_I965_G_1		0x2982
-#define PCI_CHIP_I946_GZ		0x2972
-#define PCI_CHIP_I965_GM                0x2A02
-#define PCI_CHIP_I965_GME               0x2A12
-
+#define DEBUG_BATCH	0x80000
 
 /* ================================================================
  * intel_context.c:
@@ -463,7 +432,7 @@ extern void intelInitStateFuncs( struct dd_function_table *functions );
 #define BLENDFACT_INV_CONST_ALPHA	0x0f
 #define BLENDFACT_MASK          	0x0f
 
-
+extern int intel_translate_shadow_compare_func( GLenum func );
 extern int intel_translate_compare_func( GLenum func );
 extern int intel_translate_stencil_op( GLenum op );
 extern int intel_translate_blend_factor( GLenum factor );
diff --git a/src/mesa/drivers/dri/i965/intel_decode.c b/src/mesa/drivers/dri/i965/intel_decode.c
new file mode 120000
index 0000000000..f671b6cbb1
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/intel_decode.c
@@ -0,0 +1 @@
+../intel/intel_decode.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/i965/intel_ioctl.c b/src/mesa/drivers/dri/i965/intel_ioctl.c
index 0a8e976f70..e7e736079f 100644
--- a/src/mesa/drivers/dri/i965/intel_ioctl.c
+++ b/src/mesa/drivers/dri/i965/intel_ioctl.c
@@ -115,10 +115,6 @@ void intelWaitIrq( struct intel_context *intel, int seq )
       if ( ret ) {
 	 fprintf( stderr, "%s: drmI830IrqWait: %d\n", __FUNCTION__, ret );
 
-	 if (intel->aub_file) {
-	    intel->vtbl.aub_dump_bmp( intel, intel->ctx.Visual.doubleBufferMode ? 1 : 0 );
-	 }
-
 	 exit(1);
       }
    }
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 8486086b27..0fb33e27f4 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -75,7 +75,7 @@ struct intel_mipmap_tree *intel_miptree_create( struct intel_context *intel,
    mt->width0 = width0;
    mt->height0 = height0;
    mt->depth0 = depth0;
-   mt->cpp = compressed ? 2 : cpp;
+   mt->cpp = cpp;
    mt->compressed = compressed;
 
    switch (intel->intelScreen->deviceID) {
@@ -211,7 +211,7 @@ GLuint intel_miptree_image_offset(struct intel_mipmap_tree *mt,
 
 
 
-
+extern GLuint intel_compressed_alignment(GLenum);
 /* Upload data for a particular image.
  */
 GLboolean intel_miptree_image_data(struct intel_context *intel, 
@@ -226,6 +226,17 @@ GLboolean intel_miptree_image_data(struct intel_context *intel,
    GLuint dst_offset = intel_miptree_image_offset(dst, face, level);
    const GLuint *dst_depth_offset = intel_miptree_depth_offsets(dst, level);
    GLuint i;
+   GLuint width, height, alignment;
+
+   width = dst->level[level].width;
+   height = dst->level[level].height;
+
+   if (dst->compressed) {
+       alignment = intel_compressed_alignment(dst->internal_format);
+       src_row_pitch = ((src_row_pitch + alignment - 1) & ~(alignment - 1));
+       width = ((width + alignment - 1) & ~(alignment - 1));
+       height = (height + 3) / 4;
+   }
 
    DBG("%s\n", __FUNCTION__);
    for (i = 0; i < depth; i++) {
@@ -237,8 +248,8 @@ GLboolean intel_miptree_image_data(struct intel_context *intel,
 			     src,
 			     src_row_pitch,
 			     0, 0,	/* source x,y */
-			     dst->level[level].width,
-			     dst->level[level].height))
+			     width,
+			     height))
 	 return GL_FALSE;
       src += src_image_pitch;
    }
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
index 421fcc5e51..79c1fee9c0 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_bitmap.c
@@ -168,12 +168,15 @@ do_blit_bitmap( GLcontext *ctx,
 {
    struct intel_context *intel = intel_context(ctx);
    struct intel_region *dst = intel_drawbuf_region(intel);
-   
+   GLfloat tmpColor[4];
+
    union {
       GLuint ui;
       GLubyte ub[4];
    } color;
 
+   if (!dst)
+       return GL_FALSE;
 
    if (unpack->BufferObj->Name) {
       bitmap = map_pbo(ctx, width, height, unpack, bitmap);
@@ -181,10 +184,16 @@ do_blit_bitmap( GLcontext *ctx,
 	 return GL_TRUE;	/* even though this is an error, we're done */
    }
 
-   UNCLAMPED_FLOAT_TO_CHAN(color.ub[0], ctx->Current.RasterColor[2]);
-   UNCLAMPED_FLOAT_TO_CHAN(color.ub[1], ctx->Current.RasterColor[1]);
-   UNCLAMPED_FLOAT_TO_CHAN(color.ub[2], ctx->Current.RasterColor[0]);
-   UNCLAMPED_FLOAT_TO_CHAN(color.ub[3], ctx->Current.RasterColor[3]);
+   COPY_4V(tmpColor, ctx->Current.RasterColor);
+
+   if (NEED_SECONDARY_COLOR(ctx)) {
+       ADD_3V(tmpColor, tmpColor, ctx->Current.RasterSecondaryColor);
+   }
+
+   UNCLAMPED_FLOAT_TO_CHAN(color.ub[0], tmpColor[2]);
+   UNCLAMPED_FLOAT_TO_CHAN(color.ub[1], tmpColor[1]);
+   UNCLAMPED_FLOAT_TO_CHAN(color.ub[2], tmpColor[0]);
+   UNCLAMPED_FLOAT_TO_CHAN(color.ub[3], tmpColor[3]);
 
    /* Does zoom apply to bitmaps?
     */
@@ -226,10 +235,10 @@ do_blit_bitmap( GLcontext *ctx,
       dsty = dPriv->y + (dPriv->h - dsty - height);  
       dstx = dPriv->x + dstx;
 
-      dest_rect.x1 = dstx;
-      dest_rect.y1 = dsty;
-      dest_rect.x2 = dstx + width;
-      dest_rect.y2 = dsty + height;
+      dest_rect.x1 = dstx < 0 ? 0 : dstx;
+      dest_rect.y1 = dsty < 0 ? 0 : dsty;
+      dest_rect.x2 = dstx + width < 0 ? 0 : dstx + width;
+      dest_rect.y2 = dsty + height < 0 ? 0 : dsty + height;
 
       for (i = 0; i < nbox; i++) {
          drm_clip_rect_t rect;
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_copy.c b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
index 58dc49505f..3bdf2fb479 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_copy.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_copy.c
@@ -231,6 +231,7 @@ do_blit_copypixels(GLcontext * ctx,
 
    if (intel->driDrawable->numClipRects) {
       __DRIdrawablePrivate *dPriv = intel->driDrawable;
+      __DRIdrawablePrivate *dReadPriv = intel->driReadDrawable;
       drm_clip_rect_t *box = dPriv->pClipRects;
       drm_clip_rect_t dest_rect;
       GLint nbox = dPriv->numClipRects;
@@ -262,8 +263,8 @@ do_blit_copypixels(GLcontext * ctx,
       srcy = dPriv->h - srcy - height;  
       dstx += dPriv->x;
       dsty += dPriv->y;
-      srcx += dPriv->x;
-      srcy += dPriv->y;
+      srcx += dReadPriv->x;
+      srcy += dReadPriv->y;
 
       /* Clip against the source region.  This is the only source
        * clipping we do.  Dst is clipped with cliprects below.
diff --git a/src/mesa/drivers/dri/i965/intel_regions.c b/src/mesa/drivers/dri/i965/intel_regions.c
index 835ecdd725..b78eba898f 100644
--- a/src/mesa/drivers/dri/i965/intel_regions.c
+++ b/src/mesa/drivers/dri/i965/intel_regions.c
@@ -64,7 +64,7 @@ void intel_region_unmap(struct intel_context *intel,
 {
    DBG("%s\n", __FUNCTION__);
    if (!--region->map_refcount) {
-      bmUnmapBufferAUB(intel, region->buffer, 0, 0);
+      bmUnmapBuffer(intel, region->buffer);
       region->map = NULL;
    }
 }
@@ -217,10 +217,10 @@ GLboolean intel_region_data(struct intel_context *intel,
        srcx == 0 &&
        srcy == 0) 
    {
-      return (bmBufferDataAUB(intel,
-			      dst->buffer,
-			      dst->cpp * width * dst->height,
-			      src, 0, 0, 0) == 0);
+      return (bmBufferData(intel,
+			   dst->buffer,
+			   dst->cpp * width * dst->height,
+			   src, 0) == 0);
    }
    else {
       GLubyte *map = intel_region_map(intel, dst);
diff --git a/src/mesa/drivers/dri/i965/intel_state.c b/src/mesa/drivers/dri/i965/intel_state.c
index 2e442db619..2f5467a4e4 100644
--- a/src/mesa/drivers/dri/i965/intel_state.c
+++ b/src/mesa/drivers/dri/i965/intel_state.c
@@ -38,6 +38,31 @@
 #include "intel_regions.h"
 #include "swrast/swrast.h"
 
+int intel_translate_shadow_compare_func( GLenum func )
+{
+   switch(func) {
+   case GL_NEVER: 
+       return COMPAREFUNC_ALWAYS; 
+   case GL_LESS: 
+       return COMPAREFUNC_LEQUAL; 
+   case GL_LEQUAL: 
+       return COMPAREFUNC_LESS;
+   case GL_GREATER: 
+       return COMPAREFUNC_GEQUAL; 
+   case GL_GEQUAL: 
+      return COMPAREFUNC_GREATER; 
+   case GL_NOTEQUAL: 
+      return COMPAREFUNC_EQUAL; 
+   case GL_EQUAL: 
+      return COMPAREFUNC_NOTEQUAL; 
+   case GL_ALWAYS: 
+       return COMPAREFUNC_NEVER; 
+   }
+
+   fprintf(stderr, "Unknown value in %s: %x\n", __FUNCTION__, func);
+   return COMPAREFUNC_NEVER; 
+}
+
 int intel_translate_compare_func( GLenum func )
 {
    switch(func) {
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index 44ee94614d..8c05e7cdab 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -122,6 +122,29 @@ static void intel_texture_invalidate_cb( struct intel_context *intel,
    intel_texture_invalidate( (struct intel_texture_object *) ptr );
 }
 
+#include "texformat.h"
+static GLuint intel_compressed_num_bytes(GLenum mesaFormat)
+{
+    GLuint bytes = 0;
+
+    switch (mesaFormat) {
+    case MESA_FORMAT_RGB_FXT1:
+    case MESA_FORMAT_RGBA_FXT1:
+    case MESA_FORMAT_RGB_DXT1:
+    case MESA_FORMAT_RGBA_DXT1:
+        bytes = 2;
+        break;
+
+    case MESA_FORMAT_RGBA_DXT3:
+    case MESA_FORMAT_RGBA_DXT5:
+        bytes = 4;
+    
+    default:
+        break;
+    }
+
+    return bytes;
+}
 
 /*  
  */
@@ -132,7 +155,8 @@ GLuint intel_finalize_mipmap_tree( struct intel_context *intel,
    GLuint face, i;
    GLuint nr_faces = 0;
    struct gl_texture_image *firstImage;
-
+   GLuint cpp = 0;
+   
    if( tObj == intel->frame_buffer_texobj )
       return GL_FALSE;
    
@@ -165,6 +189,12 @@ GLuint intel_finalize_mipmap_tree( struct intel_context *intel,
 
 
 
+   if (firstImage->IsCompressed) {
+       cpp = intel_compressed_num_bytes(firstImage->TexFormat->MesaFormat);
+   } else {
+       cpp = firstImage->TexFormat->TexelBytes;
+   }
+       
    /* Check tree can hold all active levels.  Check tree matches
     * target, imageFormat, etc.
     */
@@ -176,7 +206,7 @@ GLuint intel_finalize_mipmap_tree( struct intel_context *intel,
 	intelObj->mt->width0 != firstImage->Width ||
 	intelObj->mt->height0 != firstImage->Height ||
 	intelObj->mt->depth0 != firstImage->Depth ||
-	intelObj->mt->cpp != firstImage->TexFormat->TexelBytes ||
+	intelObj->mt->cpp != cpp ||
 	intelObj->mt->compressed != firstImage->IsCompressed)) 
    {
       intel_miptree_destroy(intel, intelObj->mt);
@@ -199,7 +229,7 @@ GLuint intel_finalize_mipmap_tree( struct intel_context *intel,
 					  firstImage->Width,
 					  firstImage->Height,
 					  firstImage->Depth,
-					  firstImage->TexFormat->TexelBytes,
+					  cpp,
 					  firstImage->IsCompressed);
 
       /* Tell the buffer manager that we will manage the backing
diff --git a/src/mesa/drivers/dri/i965/server/i830_common.h b/src/mesa/drivers/dri/i965/server/i830_common.h
deleted file mode 100644
index f320378c2a..0000000000
--- a/src/mesa/drivers/dri/i965/server/i830_common.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/**************************************************************************
-
-Copyright 2001 VA Linux Systems Inc., Fremont, California.
-Copyright 2002 Tungsten Graphics Inc., Cedar Park, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i830_common.h,v 1.1 2002/09/11 00:29:32 dawes Exp $ */
-
-#ifndef _I830_COMMON_H_
-#define _I830_COMMON_H_
-
-
-#define I830_NR_TEX_REGIONS 255	/* maximum due to use of chars for next/prev */
-#define I830_LOG_MIN_TEX_REGION_SIZE 14
-
-
-/* Driver specific DRM command indices
- * NOTE: these are not OS specific, but they are driver specific
- */
-#define DRM_I830_INIT                     0x00
-#define DRM_I830_FLUSH                    0x01
-#define DRM_I830_FLIP                     0x02
-#define DRM_I830_BATCHBUFFER              0x03
-#define DRM_I830_IRQ_EMIT                 0x04
-#define DRM_I830_IRQ_WAIT                 0x05
-#define DRM_I830_GETPARAM                 0x06
-#define DRM_I830_SETPARAM                 0x07
-#define DRM_I830_ALLOC                    0x08
-#define DRM_I830_FREE                     0x09
-#define DRM_I830_INIT_HEAP                0x0a
-#define DRM_I830_CMDBUFFER                0x0b
-#define DRM_I830_DESTROY_HEAP             0x0c
-#define DRM_I830_MMIO		       	  0x10
-
-typedef struct {
-   enum {
-      I830_INIT_DMA = 0x01,
-      I830_CLEANUP_DMA = 0x02,
-      I830_RESUME_DMA = 0x03
-   } func;
-   unsigned int mmio_offset;
-   int sarea_priv_offset;
-   unsigned int ring_start;
-   unsigned int ring_end;
-   unsigned int ring_size;
-   unsigned int front_offset;
-   unsigned int back_offset;
-   unsigned int depth_offset;
-   unsigned int w;
-   unsigned int h;
-   unsigned int pitch;
-   unsigned int pitch_bits;
-   unsigned int back_pitch;
-   unsigned int depth_pitch;
-   unsigned int cpp;
-   unsigned int chipset;
-} drmI830Init;
-
-typedef struct {
-	drmTextureRegion texList[I830_NR_TEX_REGIONS+1];
-        int last_upload;	/* last time texture was uploaded */
-        int last_enqueue;	/* last time a buffer was enqueued */
-        volatile int last_dispatch;	/* age of the most recently dispatched buffer */
-	int ctxOwner;		/* last context to upload state */
-	int texAge;
-        int pf_enabled;		/* is pageflipping allowed? */
-        int pf_active;               
-        int pf_current_page;	/* which buffer is being displayed? */
-        int perf_boxes;	        /* performance boxes to be displayed */   
-	int width, height;      /* screen size in pixels */
-
-	drm_handle_t front_handle;
-	int front_offset;
-	int front_size;
-
-	drm_handle_t back_handle;
-	int back_offset;
-	int back_size;
-
-	drm_handle_t depth_handle;
-	int depth_offset;
-	int depth_size;
-
-	drm_handle_t tex_handle;
-	int tex_offset;
-	int tex_size;
-	int log_tex_granularity;
-	int pitch;
-	int rotation;           /* 0, 90, 180 or 270 */
-	int rotated_offset;
-	int rotated_size;
-	int rotated_pitch;
-	int virtualX, virtualY;
-
-	unsigned int front_tiled;
-        unsigned int back_tiled;
-        unsigned int depth_tiled;
-        unsigned int rotated_tiled;
-        unsigned int rotated2_tiled;
-} drmI830Sarea;
-
-/* Flags for perf_boxes
- */
-#define I830_BOX_RING_EMPTY    0x1 /* populated by kernel */
-#define I830_BOX_FLIP          0x2 /* populated by kernel */
-#define I830_BOX_WAIT          0x4 /* populated by kernel & client */
-#define I830_BOX_TEXTURE_LOAD  0x8 /* populated by kernel */
-#define I830_BOX_LOST_CONTEXT  0x10 /* populated by client */
-
-
-typedef struct {
-   	int start;		/* agp offset */
-	int used;		/* nr bytes in use */
-	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
-        int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO*/
-	int num_cliprects;	/* mulitpass with multiple cliprects? */
-        drm_clip_rect_t *cliprects; /* pointer to userspace cliprects */
-} drmI830BatchBuffer;
-
-typedef struct {
-   	char *buf;		/* agp offset */
-	int sz; 		/* nr bytes in use */
-	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
-        int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO*/
-	int num_cliprects;	/* mulitpass with multiple cliprects? */
-        drm_clip_rect_t *cliprects; /* pointer to userspace cliprects */
-} drmI830CmdBuffer;
- 
-typedef struct {
-	int *irq_seq;
-} drmI830IrqEmit;
-
-typedef struct {
-	int irq_seq;
-} drmI830IrqWait;
-
-typedef struct {
-	int param;
-	int *value;
-} drmI830GetParam;
-
-#define I830_PARAM_IRQ_ACTIVE     1
-#define I830_PARAM_ALLOW_BATCHBUFFER   2 
-
-typedef struct {
-	int param;
-	int value;
-} drmI830SetParam;
-
-#define I830_SETPARAM_USE_MI_BATCHBUFFER_START  1
-#define I830_SETPARAM_TEX_LRU_LOG_GRANULARITY   2
-#define I830_SETPARAM_ALLOW_BATCHBUFFER         3
-
-
-/* A memory manager for regions of shared memory:
- */
-#define I830_MEM_REGION_AGP 1
-
-typedef struct {
-	int region;
-	int alignment;
-	int size;
-	int *region_offset;	/* offset from start of fb or agp */
-} drmI830MemAlloc;
-
-typedef struct {
-	int region;
-	int region_offset;
-} drmI830MemFree;
-
-typedef struct {
-	int region;
-	int size;
-	int start;	
-} drmI830MemInitHeap;
-
-typedef struct {
-	int region;
-} drmI830MemDestroyHeap;
-
-#define MMIO_READ  0
-#define MMIO_WRITE 1
-
-#define MMIO_REGS_IA_PRIMATIVES_COUNT           0
-#define MMIO_REGS_IA_VERTICES_COUNT             1
-#define MMIO_REGS_VS_INVOCATION_COUNT           2
-#define MMIO_REGS_GS_PRIMITIVES_COUNT           3
-#define MMIO_REGS_GS_INVOCATION_COUNT           4
-#define MMIO_REGS_CL_PRIMITIVES_COUNT           5
-#define MMIO_REGS_CL_INVOCATION_COUNT           6
-#define MMIO_REGS_PS_INVOCATION_COUNT           7
-#define MMIO_REGS_PS_DEPTH_COUNT                8
-
-typedef struct {
-        unsigned int read_write:1;
-        unsigned int reg:31;
-        void __user *data;
-} drmI830MMIO;
-
-#endif /* _I830_DRM_H_ */
diff --git a/src/mesa/drivers/dri/i965/server/i830_dri.h b/src/mesa/drivers/dri/i965/server/i830_dri.h
deleted file mode 100644
index 22951812ad..0000000000
--- a/src/mesa/drivers/dri/i965/server/i830_dri.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i830_dri.h,v 1.4 2002/10/30 12:52:18 alanh Exp $ */
-
-#ifndef _I830_DRI_H
-#define _I830_DRI_H
-
-#include "xf86drm.h"
-#include "i830_common.h"
-
-#define I830_MAX_DRAWABLES 256
-
-#define I830_MAJOR_VERSION 1
-#define I830_MINOR_VERSION 3
-#define I830_PATCHLEVEL 0
-
-#define I830_REG_SIZE 0x80000
-
-typedef struct _I830DRIRec {
-   drm_handle_t regs;
-   drmSize regsSize;
-
-   drmSize unused1; /* backbufferSize */
-   drm_handle_t unused2; /* backbuffer */
-
-   drmSize unused3; /* depthbufferSize */
-   drm_handle_t unused4; /* depthbuffer */
-
-   drmSize unused5; /* rotatedSize /*/
-   drm_handle_t unused6; /* rotatedbuffer */
-
-   drm_handle_t unused7; /* textures */
-   int unused8; /* textureSize */
-
-   drm_handle_t unused9; /* agp_buffers */
-   drmSize unused10; /* agp_buf_size */
-
-   int deviceID;
-   int width;
-   int height;
-   int mem;
-   int cpp;
-   int bitsPerPixel;
-
-   int unused11[8]; /* was front/back/depth/rotated offset/pitch */
-
-   int unused12; /* logTextureGranularity */
-   int unused13; /* textureOffset */
-
-   int irq;
-   int sarea_priv_offset;
-} I830DRIRec, *I830DRIPtr;
-
-typedef struct {
-   /* Nothing here yet */
-   int dummy;
-} I830ConfigPrivRec, *I830ConfigPrivPtr;
-
-typedef struct {
-   /* Nothing here yet */
-   int dummy;
-} I830DRIContextRec, *I830DRIContextPtr;
-
-
-#endif
diff --git a/src/mesa/drivers/dri/i965/server/intel.h b/src/mesa/drivers/dri/i965/server/intel.h
deleted file mode 100644
index d7858a20c8..0000000000
--- a/src/mesa/drivers/dri/i965/server/intel.h
+++ /dev/null
@@ -1,328 +0,0 @@
-#ifndef _INTEL_H_
-#define _INTEL_H_
-
-#include "xf86drm.h"		/* drm_handle_t, etc */
-
-/* Intel */
-#ifndef PCI_CHIP_I810
-#define PCI_CHIP_I810              0x7121
-#define PCI_CHIP_I810_DC100        0x7123
-#define PCI_CHIP_I810_E            0x7125
-#define PCI_CHIP_I815              0x1132
-#define PCI_CHIP_I810_BRIDGE       0x7120
-#define PCI_CHIP_I810_DC100_BRIDGE 0x7122
-#define PCI_CHIP_I810_E_BRIDGE     0x7124
-#define PCI_CHIP_I815_BRIDGE       0x1130
-#endif
-
-#define PCI_CHIP_845_G			0x2562
-#define PCI_CHIP_I830_M			0x3577
-
-#ifndef PCI_CHIP_I855_GM
-#define PCI_CHIP_I855_GM	   0x3582
-#define PCI_CHIP_I855_GM_BRIDGE	   0x3580
-#endif
-
-#ifndef PCI_CHIP_I865_G
-#define PCI_CHIP_I865_G		   0x2572
-#define PCI_CHIP_I865_G_BRIDGE	   0x2570
-#endif
-
-#ifndef PCI_CHIP_I915_G
-#define PCI_CHIP_I915_G		   0x2582
-#define PCI_CHIP_I915_G_BRIDGE	   0x2580
-#endif
-
-#ifndef PCI_CHIP_I915_GM
-#define PCI_CHIP_I915_GM	   0x2592
-#define PCI_CHIP_I915_GM_BRIDGE	   0x2590
-#endif
-
-#ifndef PCI_CHIP_E7221_G
-#define PCI_CHIP_E7221_G	   0x258A
-/* Same as I915_G_BRIDGE */
-#define PCI_CHIP_E7221_G_BRIDGE	   0x2580
-#endif
-
-#ifndef PCI_CHIP_I945_G
-#define PCI_CHIP_I945_G        0x2772
-#define PCI_CHIP_I945_G_BRIDGE 0x2770
-#endif
-
-#ifndef PCI_CHIP_I945_GM
-#define PCI_CHIP_I945_GM        0x27A2
-#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
-#endif
-
-#define IS_I810(pI810) (pI810->Chipset == PCI_CHIP_I810 ||	\
-			pI810->Chipset == PCI_CHIP_I810_DC100 || \
-			pI810->Chipset == PCI_CHIP_I810_E)
-#define IS_I815(pI810) (pI810->Chipset == PCI_CHIP_I815)
-#define IS_I830(pI810) (pI810->Chipset == PCI_CHIP_I830_M)
-#define IS_845G(pI810) (pI810->Chipset == PCI_CHIP_845_G)
-#define IS_I85X(pI810)  (pI810->Chipset == PCI_CHIP_I855_GM)
-#define IS_I852(pI810)  (pI810->Chipset == PCI_CHIP_I855_GM && (pI810->variant == I852_GM || pI810->variant == I852_GME))
-#define IS_I855(pI810)  (pI810->Chipset == PCI_CHIP_I855_GM && (pI810->variant == I855_GM || pI810->variant == I855_GME))
-#define IS_I865G(pI810) (pI810->Chipset == PCI_CHIP_I865_G)
-
-#define IS_I915G(pI810) (pI810->Chipset == PCI_CHIP_I915_G || pI810->Chipset == PCI_CHIP_E7221_G)
-#define IS_I915GM(pI810) (pI810->Chipset == PCI_CHIP_I915_GM)
-#define IS_I945G(pI810) (pI810->Chipset == PCI_CHIP_I945_G)
-#define IS_I945GM(pI810) (pI810->Chipset == PCI_CHIP_I945_GM)
-#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810))
-
-#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810))
-
-#define I830_GMCH_CTRL		0x52
-
-
-#define I830_GMCH_GMS_MASK			0x70
-#define I830_GMCH_GMS_DISABLED		0x00
-#define I830_GMCH_GMS_LOCAL			0x10
-#define I830_GMCH_GMS_STOLEN_512	0x20
-#define I830_GMCH_GMS_STOLEN_1024	0x30
-#define I830_GMCH_GMS_STOLEN_8192	0x40
-
-#define I855_GMCH_GMS_MASK			(0x7 << 4)
-#define I855_GMCH_GMS_DISABLED			0x00
-#define I855_GMCH_GMS_STOLEN_1M			(0x1 << 4)
-#define I855_GMCH_GMS_STOLEN_4M			(0x2 << 4)
-#define I855_GMCH_GMS_STOLEN_8M			(0x3 << 4)
-#define I855_GMCH_GMS_STOLEN_16M		(0x4 << 4)
-#define I855_GMCH_GMS_STOLEN_32M		(0x5 << 4)
-#define I915G_GMCH_GMS_STOLEN_48M		(0x6 << 4)
-#define I915G_GMCH_GMS_STOLEN_64M		(0x7 << 4)
-
-typedef unsigned char Bool;
-#define TRUE 1
-#define FALSE 0
-
-#define PIPE_NONE	0<<0
-#define PIPE_CRT	1<<0
-#define PIPE_TV		1<<1
-#define PIPE_DFP	1<<2
-#define PIPE_LFP	1<<3
-#define PIPE_CRT2	1<<4
-#define PIPE_TV2	1<<5
-#define PIPE_DFP2	1<<6
-#define PIPE_LFP2	1<<7
-
-typedef struct _I830MemPool *I830MemPoolPtr;
-typedef struct _I830MemRange *I830MemRangePtr;
-typedef struct _I830MemRange {
-   long Start;
-   long End;
-   long Size;
-   unsigned long Physical;
-   unsigned long Offset;		/* Offset of AGP-allocated portion */
-   unsigned long Alignment;
-   drm_handle_t Key;
-   unsigned long Pitch; // add pitch
-   I830MemPoolPtr Pool;
-} I830MemRange;
-
-typedef struct _I830MemPool {
-   I830MemRange Total;
-   I830MemRange Free;
-   I830MemRange Fixed;
-   I830MemRange Allocated;
-} I830MemPool;
-
-typedef struct {
-   int tail_mask;
-   I830MemRange mem;
-   unsigned char *virtual_start;
-   int head;
-   int tail;
-   int space;
-} I830RingBuffer;
-
-typedef struct _I830Rec {
-   unsigned char *MMIOBase;
-   unsigned char *FbBase;
-   int cpp;
-
-   unsigned int bios_version;
-
-   /* These are set in PreInit and never changed. */
-   long FbMapSize;
-   long TotalVideoRam;
-   I830MemRange StolenMemory;		/* pre-allocated memory */
-   long BIOSMemorySize;			/* min stolen pool size */
-   int BIOSMemSizeLoc;
-
-   /* These change according to what has been allocated. */
-   long FreeMemory;
-   I830MemRange MemoryAperture;
-   I830MemPool StolenPool;
-   long allocatedMemory;
-
-   /* Regions allocated either from the above pools, or from agpgart. */
-   /* for single and dual head configurations */
-   I830MemRange FrontBuffer;
-   I830MemRange FrontBuffer2;
-   I830MemRange Scratch;
-   I830MemRange Scratch2;
-
-   I830RingBuffer *LpRing;
-
-   I830MemRange BackBuffer;
-   I830MemRange DepthBuffer;
-   I830MemRange TexMem;
-   int TexGranularity;
-   I830MemRange ContextMem;
-   int drmMinor;
-   Bool have3DWindows;
-
-   Bool NeedRingBufferLow;
-   Bool allowPageFlip;
-   Bool disableTiling;
-
-   int Chipset;
-   unsigned long LinearAddr;
-   unsigned long MMIOAddr;
-
-   drmSize           registerSize;     /**< \brief MMIO register map size */
-   drm_handle_t         registerHandle;   /**< \brief MMIO register map handle */
-  //   IOADDRESS ioBase;
-   int               irq;              /**< \brief IRQ number */
-   int GttBound;
-
-   drm_handle_t ring_map;
-   unsigned int Fence[8];
-
-} I830Rec;
-
-/*
- * 12288 is set as the maximum, chosen because it is enough for
- * 1920x1440@32bpp with a 2048 pixel line pitch with some to spare.
- */
-#define I830_MAXIMUM_VBIOS_MEM		12288
-#define I830_DEFAULT_VIDEOMEM_2D	(MB(32) / 1024)
-#define I830_DEFAULT_VIDEOMEM_3D	(MB(64) / 1024)
-
-/* Flags for memory allocation function */
-#define FROM_ANYWHERE			0x00000000
-#define FROM_POOL_ONLY			0x00000001
-#define FROM_NEW_ONLY			0x00000002
-#define FROM_MASK			0x0000000f
-
-#define ALLOCATE_AT_TOP			0x00000010
-#define ALLOCATE_AT_BOTTOM		0x00000020
-#define FORCE_GAPS			0x00000040
-
-#define NEED_PHYSICAL_ADDR		0x00000100
-#define ALIGN_BOTH_ENDS			0x00000200
-#define FORCE_LOW			0x00000400
-
-#define ALLOC_NO_TILING			0x00001000
-#define ALLOC_INITIAL			0x00002000
-
-#define ALLOCATE_DRY_RUN		0x80000000
-
-/* Chipset registers for VIDEO BIOS memory RW access */
-#define _855_DRAM_RW_CONTROL 0x58
-#define _845_DRAM_RW_CONTROL 0x90
-#define DRAM_WRITE    0x33330000
-
-#define KB(x) ((x) * 1024)
-#define MB(x) ((x) * KB(1024))
-
-#define GTT_PAGE_SIZE			KB(4)
-#define ROUND_TO(x, y)			(((x) + (y) - 1) / (y) * (y))
-#define ROUND_DOWN_TO(x, y)		((x) / (y) * (y))
-#define ROUND_TO_PAGE(x)		ROUND_TO((x), GTT_PAGE_SIZE)
-#define ROUND_TO_MB(x)			ROUND_TO((x), MB(1))
-#define PRIMARY_RINGBUFFER_SIZE		KB(128)
-
-
-/* Ring buffer registers, p277, overview p19
- */
-#define LP_RING     0x2030
-#define HP_RING     0x2040
-
-#define RING_TAIL      0x00
-#define TAIL_ADDR           0x000FFFF8
-#define I830_TAIL_MASK	    0x001FFFF8
-
-#define RING_HEAD      0x04
-#define HEAD_WRAP_COUNT     0xFFE00000
-#define HEAD_WRAP_ONE       0x00200000
-#define HEAD_ADDR           0x001FFFFC
-#define I830_HEAD_MASK      0x001FFFFC
-
-#define RING_START     0x08
-#define START_ADDR          0x03FFFFF8
-#define I830_RING_START_MASK	0xFFFFF000
-
-#define RING_LEN       0x0C
-#define RING_NR_PAGES       0x001FF000 
-#define I830_RING_NR_PAGES	0x001FF000
-#define RING_REPORT_MASK    0x00000006
-#define RING_REPORT_64K     0x00000002
-#define RING_REPORT_128K    0x00000004
-#define RING_NO_REPORT      0x00000000
-#define RING_VALID_MASK     0x00000001
-#define RING_VALID          0x00000001
-#define RING_INVALID        0x00000000
-
-
-/* Fence/Tiling ranges [0..7]
- */
-#define FENCE            0x2000
-#define FENCE_NR         8
-
-#define I915G_FENCE_START_MASK	0x0ff00000
-
-#define I830_FENCE_START_MASK	0x07f80000
-
-#define FENCE_START_MASK    0x03F80000
-#define FENCE_X_MAJOR       0x00000000
-#define FENCE_Y_MAJOR       0x00001000
-#define FENCE_SIZE_MASK     0x00000700
-#define FENCE_SIZE_512K     0x00000000
-#define FENCE_SIZE_1M       0x00000100
-#define FENCE_SIZE_2M       0x00000200
-#define FENCE_SIZE_4M       0x00000300
-#define FENCE_SIZE_8M       0x00000400
-#define FENCE_SIZE_16M      0x00000500
-#define FENCE_SIZE_32M      0x00000600
-#define FENCE_SIZE_64M	    0x00000700
-#define I915G_FENCE_SIZE_1M       0x00000000
-#define I915G_FENCE_SIZE_2M       0x00000100
-#define I915G_FENCE_SIZE_4M       0x00000200
-#define I915G_FENCE_SIZE_8M       0x00000300
-#define I915G_FENCE_SIZE_16M      0x00000400
-#define I915G_FENCE_SIZE_32M      0x00000500
-#define I915G_FENCE_SIZE_64M	0x00000600
-#define I915G_FENCE_SIZE_128M	0x00000700
-#define FENCE_PITCH_1       0x00000000
-#define FENCE_PITCH_2       0x00000010
-#define FENCE_PITCH_4       0x00000020
-#define FENCE_PITCH_8       0x00000030
-#define FENCE_PITCH_16      0x00000040
-#define FENCE_PITCH_32      0x00000050
-#define FENCE_PITCH_64	    0x00000060
-#define FENCE_VALID         0x00000001
-
-#include <mmio.h>
-
-#  define MMIO_IN8(base, offset) \
-	*(volatile unsigned char *)(((unsigned char*)(base)) + (offset))
-#  define MMIO_IN32(base, offset) \
-	read_MMIO_LE32(base, offset)
-#  define MMIO_OUT8(base, offset, val) \
-	*(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val)
-#  define MMIO_OUT32(base, offset, val) \
-	*(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = CPU_TO_LE32(val)
-
-
-				/* Memory mapped register access macros */
-#define INREG8(addr)        MMIO_IN8(MMIO, addr)
-#define INREG(addr)         MMIO_IN32(MMIO, addr)
-#define OUTREG8(addr, val)  MMIO_OUT8(MMIO, addr, val)
-#define OUTREG(addr, val)   MMIO_OUT32(MMIO, addr, val)
-
-#define DSPABASE		0x70184
-
-#endif
diff --git a/src/mesa/drivers/dri/i965/server/intel_dri.c b/src/mesa/drivers/dri/i965/server/intel_dri.c
deleted file mode 100644
index 169fdbece3..0000000000
--- a/src/mesa/drivers/dri/i965/server/intel_dri.c
+++ /dev/null
@@ -1,1282 +0,0 @@
-/**
- * \file server/intel_dri.c
- * \brief File to perform the device-specific initialization tasks typically
- * done in the X server.
- *
- * Here they are converted to run in the client (or perhaps a standalone
- * process), and to work with the frame buffer device rather than the X
- * server infrastructure.
- * 
- * Copyright (C) 2006 Dave Airlie (airlied@linux.ie)
-
- Permission is hereby granted, free of charge, to any person obtaining a
- copy of this software and associated documentation files (the
- "Software"), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sub license, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
- 
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial portions
- of the Software.
- 
- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- IN NO EVENT SHALL THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR
- ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-
-#include "driver.h"
-#include "drm.h"
-
-#include "intel.h"
-#include "i830_dri.h"
-
-#include "memops.h"
-#include "pciaccess.h"
-
-static size_t drm_page_size;
-static int nextTile = 0;
-#define xf86DrvMsg(...) do {} while(0)
-
-static const int pitches[] = {
-  128 * 8,
-  128 * 16,
-  128 * 32,
-  128 * 64,
-  0
-};
-
-static Bool I830DRIDoMappings(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea);
-
-static unsigned long
-GetBestTileAlignment(unsigned long size)
-{
-   unsigned long i;
-
-   for (i = KB(512); i < size; i <<= 1)
-      ;
-
-   if (i > MB(64))
-      i = MB(64);
-
-   return i;
-}
-
-static void SetFenceRegs(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  int i;
-  unsigned char *MMIO = ctx->MMIOAddress;
-
-  for (i = 0; i < 8; i++) {
-    OUTREG(FENCE + i * 4, pI830->Fence[i]);
-    //    if (I810_DEBUG & DEBUG_VERBOSE_VGA)
-    fprintf(stderr,"Fence Register : %x\n", pI830->Fence[i]);
-  }
-}
-
-/* Tiled memory is good... really, really good...
- *
- * Need to make it less likely that we miss out on this - probably
- * need to move the frontbuffer away from the 'guarenteed' alignment
- * of the first memory segment, or perhaps allocate a discontigous
- * framebuffer to get more alignment 'sweet spots'.
- */
-static void
-SetFence(const DRIDriverContext *ctx, I830Rec *pI830,
-	 int nr, unsigned int start, unsigned int pitch,
-         unsigned int size)
-{
-   unsigned int val;
-   unsigned int fence_mask = 0;
-   unsigned int fence_pitch;
-
-   if (nr < 0 || nr > 7) {
-      fprintf(stderr,
-		 "SetFence: fence %d out of range\n",nr);
-      return;
-   }
-
-   pI830->Fence[nr] = 0;
-
-   if (IS_I9XX(pI830))
-   	fence_mask = ~I915G_FENCE_START_MASK;
-   else
-   	fence_mask = ~I830_FENCE_START_MASK;
-
-   if (start & fence_mask) {
-      fprintf(stderr,
-		 "SetFence: %d: start (0x%08x) is not %s aligned\n",
-		 nr, start, (IS_I9XX(pI830)) ? "1MB" : "512k");
-      return;
-   }
-
-   if (start % size) {
-      fprintf(stderr,
-		 "SetFence: %d: start (0x%08x) is not size (%dk) aligned\n",
-		 nr, start, size / 1024);
-      return;
-   }
-
-   if (pitch & 127) {
-      fprintf(stderr,
-		 "SetFence: %d: pitch (%d) not a multiple of 128 bytes\n",
-		 nr, pitch);
-      return;
-   }
-
-   val = (start | FENCE_X_MAJOR | FENCE_VALID);
-
-   if (IS_I9XX(pI830)) {
-   	switch (size) {
-	   case MB(1):
-      		val |= I915G_FENCE_SIZE_1M;
-      		break;
-   	   case MB(2):
-      		val |= I915G_FENCE_SIZE_2M;
-      		break;
-   	   case MB(4):
-      		val |= I915G_FENCE_SIZE_4M;
-      		break;
-   	   case MB(8):
-      		val |= I915G_FENCE_SIZE_8M;
-      		break;
-   	   case MB(16):
-      		val |= I915G_FENCE_SIZE_16M;
-      		break;
-   	   case MB(32):
-      		val |= I915G_FENCE_SIZE_32M;
-      		break;
-   	   case MB(64):
-      		val |= I915G_FENCE_SIZE_64M;
-      		break;
-   	   default:
-      		fprintf(stderr,
-		 "SetFence: %d: illegal size (%d kByte)\n", nr, size / 1024);
-      		return;
-   	}
-    } else {
-   	switch (size) {
-	   case KB(512):
-      		val |= FENCE_SIZE_512K;
-      		break;
-	   case MB(1):
-      		val |= FENCE_SIZE_1M;
-      		break;
-   	   case MB(2):
-      		val |= FENCE_SIZE_2M;
-      		break;
-   	   case MB(4):
-      		val |= FENCE_SIZE_4M;
-      		break;
-   	   case MB(8):
-      		val |= FENCE_SIZE_8M;
-      		break;
-   	   case MB(16):
-      		val |= FENCE_SIZE_16M;
-      		break;
-   	   case MB(32):
-      		val |= FENCE_SIZE_32M;
-      		break;
-   	   case MB(64):
-      		val |= FENCE_SIZE_64M;
-      		break;
-   	   default:
-      		fprintf(stderr,
-		 "SetFence: %d: illegal size (%d kByte)\n", nr, size / 1024);
-      		return;
-   	}
-   }
-
-   if (IS_I9XX(pI830))
-	fence_pitch = pitch / 512;
-   else
-	fence_pitch = pitch / 128;
-
-   switch (fence_pitch) {
-   case 1:
-      val |= FENCE_PITCH_1;
-      break;
-   case 2:
-      val |= FENCE_PITCH_2;
-      break;
-   case 4:
-      val |= FENCE_PITCH_4;
-      break;
-   case 8:
-      val |= FENCE_PITCH_8;
-      break;
-   case 16:
-      val |= FENCE_PITCH_16;
-      break;
-   case 32:
-      val |= FENCE_PITCH_32;
-      break;
-   case 64:
-      val |= FENCE_PITCH_64;
-      break;
-   default:
-      fprintf(stderr,
-		 "SetFence: %d: illegal pitch (%d)\n", nr, pitch);
-      return;
-   }
-
-   pI830->Fence[nr] = val;
-}
-
-static Bool
-MakeTiles(const DRIDriverContext *ctx, I830Rec *pI830, I830MemRange *pMem)
-{
-   int pitch, ntiles, i;
-
-   pitch = pMem->Pitch * ctx->cpp;
-   /*
-    * Simply try to break the region up into at most four pieces of size
-    * equal to the alignment.
-    */
-   ntiles = ROUND_TO(pMem->Size, pMem->Alignment) / pMem->Alignment;
-   if (ntiles >= 4) {
-      return FALSE;
-   }
-
-   for (i = 0; i < ntiles; i++, nextTile++) {
-     SetFence(ctx, pI830, nextTile, pMem->Start + i * pMem->Alignment,
-	       pitch, pMem->Alignment);
-   }
-   return TRUE;
-}
-
-static void I830SetupMemoryTiling(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  int i;
-
-  /* Clear out */
-  for (i = 0; i < 8; i++)
-    pI830->Fence[i] = 0;
-  
-  nextTile = 0;
-
-  if (pI830->BackBuffer.Alignment >= KB(512)) {
-    if (MakeTiles(ctx, pI830, &(pI830->BackBuffer))) {
-      fprintf(stderr,
-		 "Activating tiled memory for the back buffer.\n");
-    } else {
-      fprintf(stderr,
-		 "MakeTiles failed for the back buffer.\n");
-      pI830->allowPageFlip = FALSE;
-    }
-  }
-  
-  if (pI830->DepthBuffer.Alignment >= KB(512)) {
-    if (MakeTiles(ctx, pI830, &(pI830->DepthBuffer))) {
-      fprintf(stderr,
-		 "Activating tiled memory for the depth buffer.\n");
-    } else {
-      fprintf(stderr,
-		 "MakeTiles failed for the depth buffer.\n");
-    }
-  }
-
-  return;
-}
-
-static int I830DetectMemory(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  struct pci_device host_bridge;
-  uint32_t gmch_ctrl;
-  int memsize = 0;
-  int range;
-
-  memset(&host_bridge, 0, sizeof(host_bridge));
-
-  pci_device_cfg_read_u32(&host_bridge, &gmch_ctrl, I830_GMCH_CTRL);
-  
-  /* We need to reduce the stolen size, by the GTT and the popup.
-   * The GTT varying according the the FbMapSize and the popup is 4KB */
-  range = (ctx->shared.fbSize / (1024*1024)) + 4;
-
-   if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
-      switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
-      case I855_GMCH_GMS_STOLEN_1M:
-	 memsize = MB(1) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_4M:
-	 memsize = MB(4) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_8M:
-	 memsize = MB(8) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_16M:
-	 memsize = MB(16) - KB(range);
-	 break;
-      case I855_GMCH_GMS_STOLEN_32M:
-	 memsize = MB(32) - KB(range);
-	 break;
-      case I915G_GMCH_GMS_STOLEN_48M:
-	 if (IS_I9XX(pI830))
-	    memsize = MB(48) - KB(range);
-	 break;
-      case I915G_GMCH_GMS_STOLEN_64M:
-	 if (IS_I9XX(pI830))
-	    memsize = MB(64) - KB(range);
-	 break;
-      }
-   } else {
-      switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
-      case I830_GMCH_GMS_STOLEN_512:
-	 memsize = KB(512) - KB(range);
-	 break;
-      case I830_GMCH_GMS_STOLEN_1024:
-	 memsize = MB(1) - KB(range);
-	 break;
-      case I830_GMCH_GMS_STOLEN_8192:
-	 memsize = MB(8) - KB(range);
-	 break;
-      case I830_GMCH_GMS_LOCAL:
-	 memsize = 0;
-	 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
-		    "Local memory found, but won't be used.\n");
-	 break;
-      }
-   }
-   if (memsize > 0) {
-     fprintf(stderr,
-		 "detected %d kB stolen memory.\n", memsize / 1024);
-   } else {
-     fprintf(stderr,
-		 "no video memory detected.\n");
-   }
-   return memsize;
-}
-
-static int AgpInit(const DRIDriverContext *ctx, I830Rec *info)
-{
-  unsigned long mode = 0x4;
-
-  if (drmAgpAcquire(ctx->drmFD) < 0) {
-    fprintf(stderr, "[gart] AGP not available\n");
-    return 0;
-  }
-  
-  if (drmAgpEnable(ctx->drmFD, mode) < 0) {
-    fprintf(stderr, "[gart] AGP not enabled\n");
-    drmAgpRelease(ctx->drmFD);
-    return 0;
-  }
-  else
-    fprintf(stderr, "[gart] AGP enabled at %dx\n", ctx->agpmode);
-
-  return 1;
-}
-
-/*
- * Allocate memory from the given pool.  Grow the pool if needed and if
- * possible.
- */
-static unsigned long
-AllocFromPool(const DRIDriverContext *ctx, I830Rec *pI830, 
-	      I830MemRange *result, I830MemPool *pool,
-	      long size, unsigned long alignment, int flags)
-{
-   long needed, start, end;
-
-   if (!result || !pool || !size)
-      return 0;
-
-   /* Calculate how much space is needed. */
-   if (alignment <= GTT_PAGE_SIZE)
-      needed = size;
-   else {
-	 start = ROUND_TO(pool->Free.Start, alignment);
-	 end = ROUND_TO(start + size, alignment);
-	 needed = end - pool->Free.Start;
-   }
-   if (needed > pool->Free.Size) {
-     return 0;
-   }
-
-   result->Start = ROUND_TO(pool->Free.Start, alignment);
-   pool->Free.Start += needed;
-   result->End = pool->Free.Start;
-
-   pool->Free.Size = pool->Free.End - pool->Free.Start;
-   result->Size = result->End - result->Start;
-   result->Pool = pool;
-   result->Alignment = alignment;
-   return needed;
-}
-
-static unsigned long AllocFromAGP(const DRIDriverContext *ctx, I830Rec *pI830, long size, unsigned long alignment, I830MemRange  *result)
-{
-   unsigned long start, end;
-   unsigned long newApStart, newApEnd;
-   int ret;
-   if (!result || !size)
-      return 0;
-   
-   if (!alignment)
-     alignment = 4;
-
-   start = ROUND_TO(pI830->MemoryAperture.Start, alignment);
-   end = ROUND_TO(start + size, alignment);
-   newApStart = end;
-   newApEnd = pI830->MemoryAperture.End;
-
-   ret=drmAgpAlloc(ctx->drmFD, size, 0, &(result->Physical), (drm_handle_t *)&(result->Key));
-   
-   if (ret)
-   {
-     fprintf(stderr,"drmAgpAlloc failed %d\n", ret);
-     return 0;
-   }
-   pI830->allocatedMemory += size;
-   pI830->MemoryAperture.Start = newApStart;
-   pI830->MemoryAperture.End = newApEnd;
-   pI830->MemoryAperture.Size = newApEnd - newApStart;
-   //   pI830->FreeMemory -= size;
-   result->Start = start;
-   result->End = start + size;
-   result->Size = size;
-   result->Offset = start;
-   result->Alignment = alignment;
-   result->Pool = NULL;
-  
-   return size;
-}
-
-unsigned long
-I830AllocVidMem(const DRIDriverContext *ctx, I830Rec *pI830, I830MemRange *result, I830MemPool *pool, long size, unsigned long alignment, int flags)
-{
-  int ret;
-
-  if (!result)
-    return 0;
-
-   /* Make sure these are initialised. */
-   result->Size = 0;
-   result->Key = -1;
-
-   if (!size) {
-      return 0;
-   }
-
-   if (pool->Free.Size < size)
-     return AllocFromAGP(ctx, pI830, size, alignment, result);
-   else
-   {
-     ret = AllocFromPool(ctx, pI830, result, pool, size, alignment, flags);
-
-     if (ret==0)
-       return AllocFromAGP(ctx, pI830, size, alignment, result);
-     return ret;
-   }
-}
-
-static Bool BindAgpRange(const DRIDriverContext *ctx, I830MemRange *mem)
-{
-  if (!mem)
-    return FALSE;
-  
-  if (mem->Key == -1)
-    return TRUE;
-
-  return !drmAgpBind(ctx->drmFD, mem->Key, mem->Offset);
-}
-
-/* simple memory allocation routines needed */
-/* put ring buffer in low memory */
-/* need to allocate front, back, depth buffers aligned correctly,
-   allocate ring buffer, 
-*/
-
-/* */
-static Bool
-I830AllocateMemory(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  unsigned long size, ret;
-  unsigned long lines, lineSize, align;
-
-  /* allocate ring buffer */
-  memset(pI830->LpRing, 0, sizeof(I830RingBuffer));
-  pI830->LpRing->mem.Key = -1;
-
-  size = PRIMARY_RINGBUFFER_SIZE;
-  
-  ret = I830AllocVidMem(ctx, pI830, &pI830->LpRing->mem, &pI830->StolenPool, size, 0x1000, 0);
-  
-  if (ret != size)
-  {
-    fprintf(stderr,"unable to allocate ring buffer %ld\n", ret);
-    return FALSE;
-  }
-
-  pI830->LpRing->tail_mask = pI830->LpRing->mem.Size - 1;
-
-  
-  /* allocate front buffer */
-  memset(&(pI830->FrontBuffer), 0, sizeof(pI830->FrontBuffer));
-  pI830->FrontBuffer.Key = -1;
-  pI830->FrontBuffer.Pitch = ctx->shared.virtualWidth;
-
-  align = KB(512);  
-
-  lineSize = ctx->shared.virtualWidth * ctx->cpp;
-  lines = (ctx->shared.virtualHeight + 15) / 16 * 16;
-  size = lineSize * lines;
-  size = ROUND_TO_PAGE(size);
-
-  align = GetBestTileAlignment(size);
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->FrontBuffer, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate front buffer %ld\n", ret);
-    return FALSE;
-  }
-
-  memset(&(pI830->BackBuffer), 0, sizeof(pI830->BackBuffer));
-  pI830->BackBuffer.Key = -1;
-  pI830->BackBuffer.Pitch = ctx->shared.virtualWidth;
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->BackBuffer, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate back buffer %ld\n", ret);
-    return FALSE;
-  }
-  
-  memset(&(pI830->DepthBuffer), 0, sizeof(pI830->DepthBuffer));
-  pI830->DepthBuffer.Key = -1;
-  pI830->DepthBuffer.Pitch = ctx->shared.virtualWidth;
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->DepthBuffer, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate depth buffer %ld\n", ret);
-    return FALSE;
-  }
-
-  memset(&(pI830->ContextMem), 0, sizeof(pI830->ContextMem));
-  pI830->ContextMem.Key = -1;
-  size = KB(32);
-
-  ret = I830AllocVidMem(ctx, pI830, &pI830->ContextMem, &pI830->StolenPool, size, align, 0);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate context buffer %ld\n", ret);
-    return FALSE;
-  }
-  
-  memset(&(pI830->TexMem), 0, sizeof(pI830->TexMem));
-  pI830->TexMem.Key = -1;
-
-  size = 32768 * 1024;
-  ret = AllocFromAGP(ctx, pI830, size, align, &pI830->TexMem);
-  if (ret < size)
-  {
-    fprintf(stderr,"unable to allocate texture memory %ld\n", ret);
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-static Bool
-I830BindMemory(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  if (!BindAgpRange(ctx, &pI830->LpRing->mem))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->FrontBuffer))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->BackBuffer))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->DepthBuffer))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->ContextMem))
-    return FALSE;
-  if (!BindAgpRange(ctx, &pI830->TexMem))
-    return FALSE;
-
-  return TRUE;
-}
-
-static Bool
-I830CleanupDma(const DRIDriverContext *ctx)
-{
-   drmI830Init info;
-
-   memset(&info, 0, sizeof(drmI830Init));
-   info.func = I830_CLEANUP_DMA;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_I830_INIT,
-		       &info, sizeof(drmI830Init))) {
-     fprintf(stderr, "I830 Dma Cleanup Failed\n");
-      return FALSE;
-   }
-
-   return TRUE;
-}
-
-static Bool
-I830InitDma(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-   I830RingBuffer *ring = pI830->LpRing;
-   drmI830Init info;
-
-   memset(&info, 0, sizeof(drmI830Init));
-   info.func = I830_INIT_DMA;
-
-   info.ring_start = ring->mem.Start + pI830->LinearAddr;
-   info.ring_end = ring->mem.End + pI830->LinearAddr;
-   info.ring_size = ring->mem.Size;
-
-   info.mmio_offset = (unsigned int)ctx->MMIOStart;
-
-   info.sarea_priv_offset = sizeof(drm_sarea_t);
-
-   info.front_offset = pI830->FrontBuffer.Start;
-   info.back_offset = pI830->BackBuffer.Start;
-   info.depth_offset = pI830->DepthBuffer.Start;
-   info.w = ctx->shared.virtualWidth;
-   info.h = ctx->shared.virtualHeight;
-   info.pitch = ctx->shared.virtualWidth;
-   info.back_pitch = pI830->BackBuffer.Pitch;
-   info.depth_pitch = pI830->DepthBuffer.Pitch;
-   info.cpp = ctx->cpp;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_I830_INIT,
-		       &info, sizeof(drmI830Init))) {
-      fprintf(stderr,
-		 "I830 Dma Initialization Failed\n");
-      return FALSE;
-   }
-
-   return TRUE;
-}
-
-static int I830CheckDRMVersion( const DRIDriverContext *ctx,
-				  I830Rec *pI830 )
-{
-   drmVersionPtr  version;
-
-   version = drmGetVersion(ctx->drmFD);
-
-   if (version) {
-     int req_minor, req_patch;
-
-     req_minor = 4;
-     req_patch = 0;	
-
-     if (version->version_major != 1 ||
-	 version->version_minor < req_minor ||
-	 (version->version_minor == req_minor && 
-	  version->version_patchlevel < req_patch)) {
-       /* Incompatible drm version */
-       fprintf(stderr,
-	       "[dri] I830DRIScreenInit failed because of a version "
-	       "mismatch.\n"
-	       "[dri] i915.o kernel module version is %d.%d.%d "
-	       "but version 1.%d.%d or newer is needed.\n"
-	       "[dri] Disabling DRI.\n",
-	       version->version_major,
-	       version->version_minor,
-	       version->version_patchlevel,
-	       req_minor,
-	       req_patch);
-       drmFreeVersion(version);
-       return 0;
-     }
-     
-     pI830->drmMinor = version->version_minor;
-     drmFreeVersion(version);
-   }
-   return 1;
-}
-
-static void
-I830SetRingRegs(const DRIDriverContext *ctx, I830Rec *pI830)
-{
-  unsigned int itemp;
-  unsigned char *MMIO = ctx->MMIOAddress;
-
-   OUTREG(LP_RING + RING_LEN, 0);
-   OUTREG(LP_RING + RING_TAIL, 0);
-   OUTREG(LP_RING + RING_HEAD, 0);
-
-   if ((long)(pI830->LpRing->mem.Start & I830_RING_START_MASK) !=
-       pI830->LpRing->mem.Start) {
-      fprintf(stderr,
-		 "I830SetRingRegs: Ring buffer start (%lx) violates its "
-		 "mask (%x)\n", pI830->LpRing->mem.Start, I830_RING_START_MASK);
-   }
-   /* Don't care about the old value.  Reserved bits must be zero anyway. */
-   itemp = pI830->LpRing->mem.Start & I830_RING_START_MASK;
-   OUTREG(LP_RING + RING_START, itemp);
-
-   if (((pI830->LpRing->mem.Size - 4096) & I830_RING_NR_PAGES) !=
-       pI830->LpRing->mem.Size - 4096) {
-      fprintf(stderr,
-		 "I830SetRingRegs: Ring buffer size - 4096 (%lx) violates its "
-		 "mask (%x)\n", pI830->LpRing->mem.Size - 4096,
-		 I830_RING_NR_PAGES);
-   }
-   /* Don't care about the old value.  Reserved bits must be zero anyway. */
-   itemp = (pI830->LpRing->mem.Size - 4096) & I830_RING_NR_PAGES;
-   itemp |= (RING_NO_REPORT | RING_VALID);
-   OUTREG(LP_RING + RING_LEN, itemp);
-
-   pI830->LpRing->head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK;
-   pI830->LpRing->tail = INREG(LP_RING + RING_TAIL);
-   pI830->LpRing->space = pI830->LpRing->head - (pI830->LpRing->tail + 8);
-   if (pI830->LpRing->space < 0)
-      pI830->LpRing->space += pI830->LpRing->mem.Size;
-
-   SetFenceRegs(ctx, pI830);
-   
-   /* RESET THE DISPLAY PIPE TO POINT TO THE FRONTBUFFER - hacky
-      hacky hacky */
-   OUTREG(DSPABASE, pI830->FrontBuffer.Start + pI830->LinearAddr);
-
-}
-
-static Bool
-I830SetParam(const DRIDriverContext *ctx, int param, int value)
-{
-   drmI830SetParam sp;
-
-   memset(&sp, 0, sizeof(sp));
-   sp.param = param;
-   sp.value = value;
-
-   if (drmCommandWrite(ctx->drmFD, DRM_I830_SETPARAM, &sp, sizeof(sp))) {
-      fprintf(stderr, "I830 SetParam Failed\n");
-      return FALSE;
-   }
-
-   return TRUE;
-}
-
-static Bool
-I830DRIMapScreenRegions(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-   fprintf(stderr,
-              "[drm] Mapping front buffer\n");
-
-   if (drmAddMap(ctx->drmFD,
-                 (drm_handle_t)(sarea->front_offset + pI830->LinearAddr),
-                 sarea->front_size,
-                 DRM_FRAME_BUFFER,  /*DRM_AGP,*/
-                 0,
-                 &sarea->front_handle) < 0) {
-     fprintf(stderr,
-	     "[drm] drmAddMap(front_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   ctx->shared.hFrameBuffer = sarea->front_handle;
-   ctx->shared.fbSize = sarea->front_size;
-   fprintf(stderr, "[drm] Front Buffer = 0x%08x\n",
-	   sarea->front_handle);
-
-   if (drmAddMap(ctx->drmFD,
-                 (drm_handle_t)(sarea->back_offset),
-                 sarea->back_size, DRM_AGP, 0,
-                 &sarea->back_handle) < 0) {
-      fprintf(stderr,
-                 "[drm] drmAddMap(back_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   fprintf(stderr, "[drm] Back Buffer = 0x%08x\n",
-              sarea->back_handle);
-
-   if (drmAddMap(ctx->drmFD,
-                 (drm_handle_t)sarea->depth_offset,
-                 sarea->depth_size, DRM_AGP, 0,
-                 &sarea->depth_handle) < 0) {
-      fprintf(stderr,
-                 "[drm] drmAddMap(depth_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   fprintf(stderr, "[drm] Depth Buffer = 0x%08x\n",
-              sarea->depth_handle);
-
-   if (drmAddMap(ctx->drmFD,
-		 (drm_handle_t)sarea->tex_offset,
-		 sarea->tex_size, DRM_AGP, 0,
-		 &sarea->tex_handle) < 0) {
-      fprintf(stderr,
-		 "[drm] drmAddMap(tex_handle) failed. Disabling DRI\n");
-      return FALSE;
-   }
-   fprintf(stderr, "[drm] textures = 0x%08x\n",
-	      sarea->tex_handle);
-
-   return TRUE;
-}
-
-
-static void
-I830DRIUnmapScreenRegions(const DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-#if 1
-   if (sarea->front_handle) {
-      drmRmMap(ctx->drmFD, sarea->front_handle);
-      sarea->front_handle = 0;
-   }
-#endif
-   if (sarea->back_handle) {
-      drmRmMap(ctx->drmFD, sarea->back_handle);
-      sarea->back_handle = 0;
-   }
-   if (sarea->depth_handle) {
-      drmRmMap(ctx->drmFD, sarea->depth_handle);
-      sarea->depth_handle = 0;
-   }
-   if (sarea->tex_handle) {
-      drmRmMap(ctx->drmFD, sarea->tex_handle);
-      sarea->tex_handle = 0;
-   }
-}
-
-static void
-I830InitTextureHeap(const DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-   /* Start up the simple memory manager for agp space */
-   drmI830MemInitHeap drmHeap;
-   drmHeap.region = I830_MEM_REGION_AGP;
-   drmHeap.start  = 0;
-   drmHeap.size   = sarea->tex_size;
-      
-   if (drmCommandWrite(ctx->drmFD, DRM_I830_INIT_HEAP,
-			  &drmHeap, sizeof(drmHeap))) {
-      fprintf(stderr,
-		    "[drm] Failed to initialized agp heap manager\n");
-   } else {
-      fprintf(stderr,
-		    "[drm] Initialized kernel agp heap manager, %d\n",
-		    sarea->tex_size);
-
-      I830SetParam(ctx, I830_SETPARAM_TEX_LRU_LOG_GRANULARITY, 
-		      sarea->log_tex_granularity);
-   }
-}
-
-static Bool
-I830DRIDoMappings(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-  if (drmAddMap(ctx->drmFD,
-		(drm_handle_t)pI830->LpRing->mem.Start,
-		pI830->LpRing->mem.Size, DRM_AGP, 0,
-		&pI830->ring_map) < 0) {
-    fprintf(stderr,
-	    "[drm] drmAddMap(ring_map) failed. Disabling DRI\n");
-    return FALSE;
-  }
-  fprintf(stderr, "[drm] ring buffer = 0x%08x\n",
-	  pI830->ring_map);
-
-  if (I830InitDma(ctx, pI830) == FALSE) {
-    return FALSE;
-  }
-  
-   /* init to zero to be safe */
-
-  I830DRIMapScreenRegions(ctx, pI830, sarea);
-  I830InitTextureHeap(ctx, pI830, sarea);
-
-   if (ctx->pciDevice != PCI_CHIP_845_G &&
-       ctx->pciDevice != PCI_CHIP_I830_M) {
-      I830SetParam(ctx, I830_SETPARAM_USE_MI_BATCHBUFFER_START, 1 );
-   }
-
-   /* Okay now initialize the dma engine */
-   {
-      pI830->irq = drmGetInterruptFromBusID(ctx->drmFD,
-					    ctx->pciBus,
-					    ctx->pciDevice,
-					    ctx->pciFunc);
-
-      if (drmCtlInstHandler(ctx->drmFD, pI830->irq)) {
-	 fprintf(stderr,
-		    "[drm] failure adding irq handler\n");
-	 pI830->irq = 0;
-	 return FALSE;
-      }
-      else
-	 fprintf(stderr,
-		    "[drm] dma control initialized, using IRQ %d\n",
-		    pI830->irq);
-   }
-
-   fprintf(stderr, "[dri] visual configs initialized\n");
-
-   return TRUE;
-}
-
-static Bool
-I830ClearScreen(DRIDriverContext *ctx, I830Rec *pI830, drmI830Sarea *sarea)
-{
-  /* need to drmMap front and back buffers and zero them */
-  drmAddress map_addr;
-  int ret;
-
-  ret = drmMap(ctx->drmFD,
-	       sarea->front_handle,
-	       sarea->front_size,
-	       &map_addr);
-
-  if (ret)
-  {
-    fprintf(stderr, "Unable to map front buffer\n");
-    return FALSE;
-  }
-
-  drimemsetio((char *)map_addr,
-	      0,
-	      sarea->front_size);
-  drmUnmap(map_addr, sarea->front_size);
-
-
-  ret = drmMap(ctx->drmFD,
-	       sarea->back_handle,
-	       sarea->back_size,
-	       &map_addr);
-
-  if (ret)
-  {
-    fprintf(stderr, "Unable to map back buffer\n");
-    return FALSE;
-  }
-
-  drimemsetio((char *)map_addr,
-	      0,
-	      sarea->back_size);
-  drmUnmap(map_addr, sarea->back_size);
-
-  return TRUE;
-}
-
-static Bool
-I830ScreenInit(DRIDriverContext *ctx, I830Rec *pI830)
-		  
-{
-   I830DRIPtr pI830DRI;
-   drmI830Sarea *pSAREAPriv;
-   int err;
-      
-   drm_page_size = getpagesize();   
-
-   pI830->registerSize = ctx->MMIOSize;
-   /* This is a hack for now.  We have to have more than a 4k page here
-    * because of the size of the state.  However, the state should be
-    * in a per-context mapping.  This will be added in the Mesa 3.5 port
-    * of the I830 driver.
-    */
-   ctx->shared.SAREASize = SAREA_MAX;
-
-   /* Note that drmOpen will try to load the kernel module, if needed. */
-   ctx->drmFD = drmOpen("i915", NULL );
-   if (ctx->drmFD < 0) {
-      fprintf(stderr, "[drm] drmOpen failed\n");
-      return 0;
-   }
-
-   if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
-      fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
-	      ctx->drmFD, ctx->pciBusID, strerror(-err));
-      return 0;
-   }
-
-   if (drmAddMap( ctx->drmFD,
-		  0,
-		  ctx->shared.SAREASize,
-		  DRM_SHM,
-		  DRM_CONTAINS_LOCK,
-		  &ctx->shared.hSAREA) < 0)
-   {
-     fprintf(stderr, "[drm] drmAddMap failed\n");
-     return 0;
-   }
-
-   fprintf(stderr, "[drm] added %d byte SAREA at 0x%08x\n",
-	   ctx->shared.SAREASize, ctx->shared.hSAREA);
-   
-   if (drmMap( ctx->drmFD,
-	       ctx->shared.hSAREA,
-	       ctx->shared.SAREASize,
-	       (drmAddressPtr)(&ctx->pSAREA)) < 0)
-   {
-      fprintf(stderr, "[drm] drmMap failed\n");
-      return 0;
-   
-   }
-   
-   memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
-   fprintf(stderr, "[drm] mapped SAREA 0x%08x to %p, size %d\n",
-	   ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-   
-
-   if (drmAddMap(ctx->drmFD, 
-		 ctx->MMIOStart,
-		 ctx->MMIOSize,
-		 DRM_REGISTERS, 
-		 DRM_READ_ONLY, 
-		 &pI830->registerHandle) < 0) {
-      fprintf(stderr, "[drm] drmAddMap mmio failed\n");	
-      return 0;
-   }
-   fprintf(stderr,
-	   "[drm] register handle = 0x%08x\n", pI830->registerHandle);
-
-
-   if (!I830CheckDRMVersion(ctx, pI830)) {
-     return FALSE;
-   }
-
-   /* Create a 'server' context so we can grab the lock for
-    * initialization ioctls.
-    */
-   if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
-      fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
-      return 0;
-   }
-
-   DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0); 
-
-   /* Initialize the SAREA private data structure */
-   pSAREAPriv = (drmI830Sarea *)(((char*)ctx->pSAREA) + 
-				 sizeof(drm_sarea_t));
-   memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
-
-   pI830->StolenMemory.Size = I830DetectMemory(ctx, pI830);
-   pI830->StolenMemory.Start = 0;
-   pI830->StolenMemory.End = pI830->StolenMemory.Size;
-
-   pI830->MemoryAperture.Start = pI830->StolenMemory.End;
-   pI830->MemoryAperture.End = KB(40000);
-   pI830->MemoryAperture.Size = pI830->MemoryAperture.End - pI830->MemoryAperture.Start;
-
-   pI830->StolenPool.Fixed = pI830->StolenMemory;
-   pI830->StolenPool.Total = pI830->StolenMemory;
-   pI830->StolenPool.Free = pI830->StolenPool.Total;
-   pI830->FreeMemory = pI830->StolenPool.Total.Size;
-
-   if (!AgpInit(ctx, pI830))
-     return FALSE;
-
-   if (I830AllocateMemory(ctx, pI830) == FALSE)
-   {
-     return FALSE;
-   }
-
-   if (I830BindMemory(ctx, pI830) == FALSE)
-   {
-     return FALSE;
-   }
-
-   pSAREAPriv->front_offset = pI830->FrontBuffer.Start;
-   pSAREAPriv->front_size = pI830->FrontBuffer.Size;
-   pSAREAPriv->width = ctx->shared.virtualWidth;
-   pSAREAPriv->height = ctx->shared.virtualHeight;
-   pSAREAPriv->pitch = ctx->shared.virtualWidth;
-   pSAREAPriv->virtualX = ctx->shared.virtualWidth;
-   pSAREAPriv->virtualY = ctx->shared.virtualHeight;
-   pSAREAPriv->back_offset = pI830->BackBuffer.Start;
-   pSAREAPriv->back_size = pI830->BackBuffer.Size;
-   pSAREAPriv->depth_offset = pI830->DepthBuffer.Start;
-   pSAREAPriv->depth_size = pI830->DepthBuffer.Size;
-   pSAREAPriv->tex_offset = pI830->TexMem.Start;
-   pSAREAPriv->tex_size = pI830->TexMem.Size;
-   pSAREAPriv->log_tex_granularity = pI830->TexGranularity;
-
-   ctx->driverClientMsg = malloc(sizeof(I830DRIRec));
-   ctx->driverClientMsgSize = sizeof(I830DRIRec);
-   pI830DRI = (I830DRIPtr)ctx->driverClientMsg;
-   pI830DRI->deviceID = pI830->Chipset;
-   pI830DRI->regsSize = I830_REG_SIZE;
-   pI830DRI->width = ctx->shared.virtualWidth;
-   pI830DRI->height = ctx->shared.virtualHeight;
-   pI830DRI->mem = ctx->shared.fbSize;
-   pI830DRI->cpp = ctx->cpp;
-   pI830DRI->backOffset = pI830->BackBuffer.Start;
-   pI830DRI->backPitch = pI830->BackBuffer.Pitch; 
-
-   pI830DRI->depthOffset = pI830->DepthBuffer.Start;
-   pI830DRI->depthPitch = pI830->DepthBuffer.Pitch; 
-
-   pI830DRI->fbOffset = pI830->FrontBuffer.Start;
-   pI830DRI->fbStride = pI830->FrontBuffer.Pitch;
-
-   pI830DRI->bitsPerPixel = ctx->bpp;
-   pI830DRI->sarea_priv_offset = sizeof(drm_sarea_t);
-   
-   err = I830DRIDoMappings(ctx, pI830, pSAREAPriv);
-   if (err == FALSE)
-       return FALSE;
-
-   I830SetupMemoryTiling(ctx, pI830);
-
-   /* Quick hack to clear the front & back buffers.  Could also use
-    * the clear ioctl to do this, but would need to setup hw state
-    * first.
-    */
-   I830ClearScreen(ctx, pI830, pSAREAPriv);
-
-   I830SetRingRegs(ctx, pI830);
-
-   return TRUE;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa radeonValidateMode().
- */
-static int i830ValidateMode( const DRIDriverContext *ctx )
-{
-  return 1;
-}
-
-/**
- * \brief Examine mode returned by fbdev.
- * 
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa i810ValidateMode().
- */
-static int i830PostValidateMode( const DRIDriverContext *ctx )
-{
-  I830Rec *pI830 = ctx->driverPrivate;
-
-  I830SetRingRegs(ctx, pI830);
-  return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls I810ScreenInit() for the screen initialization.
- * 
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int i830InitFBDev( DRIDriverContext *ctx )
-{
-  I830Rec *pI830 = calloc(1, sizeof(I830Rec));
-  int i;
-
-   {
-      int  dummy = ctx->shared.virtualWidth;
-
-      switch (ctx->bpp / 8) {
-      case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
-      case 2: dummy = (ctx->shared.virtualWidth +  31) &  ~31; break;
-      case 3:
-      case 4: dummy = (ctx->shared.virtualWidth +  15) &  ~15; break;
-      }
-
-      ctx->shared.virtualWidth = dummy;
-      ctx->shared.Width = ctx->shared.virtualWidth;
-   }
-
-
-   for (i = 0; pitches[i] != 0; i++) {
-     if (pitches[i] >= ctx->shared.virtualWidth) {
-       ctx->shared.virtualWidth = pitches[i];
-       break;
-     }
-   }
-
-   ctx->driverPrivate = (void *)pI830;
-   
-   pI830->LpRing = calloc(1, sizeof(I830RingBuffer));
-   pI830->Chipset = ctx->chipset;
-   pI830->LinearAddr = ctx->FBStart;
-
-   if (!I830ScreenInit( ctx, pI830 ))
-      return 0;
-
-   
-   return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void i830HaltFBDev( DRIDriverContext *ctx )
-{
-  drmI830Sarea *pSAREAPriv;
-  I830Rec *pI830 = ctx->driverPrivate;
-
-   if (pI830->irq) {
-       drmCtlUninstHandler(ctx->drmFD);
-       pI830->irq = 0;   }
-
-   I830CleanupDma(ctx);
-
-  pSAREAPriv = (drmI830Sarea *)(((char*)ctx->pSAREA) + 
-				sizeof(drm_sarea_t));
-
-  I830DRIUnmapScreenRegions(ctx, pI830, pSAREAPriv);
-  drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
-  drmClose(ctx->drmFD);
-  
-  if (ctx->driverPrivate) {
-    free(ctx->driverPrivate);
-    ctx->driverPrivate = 0;
-  }
-}
-
-
-extern void i810NotifyFocus( int );
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-const struct DRIDriverRec __driDriver = {
-   i830ValidateMode,
-   i830PostValidateMode,
-   i830InitFBDev,
-   i830HaltFBDev,
-   NULL,//I830EngineShutdown,
-   NULL, //I830EngineRestore,  
-#ifndef _EMBEDDED
-   0,
-#else
-   i810NotifyFocus, 
-#endif
-};