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authorEric Anholt <eric@anholt.net>2010-12-03 12:20:02 -0800
committerEric Anholt <eric@anholt.net>2010-12-06 00:14:22 -0800
commitd1ead22d1bc2931e46410cd7367e48656135d63c (patch)
tree755779f749345deae67e35357bd6c86b398800b5 /src/mesa/drivers/dri/i965
parentad35528944960f1619e0a9491164c848b333e6cf (diff)
i965: Fix up 16-wide gen6 FB writes after various refactoring.
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_emit.c17
1 files changed, 8 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 8b255b1c61..6e8f08c14d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -1416,7 +1416,6 @@ void emit_fb_write(struct brw_wm_compile *c,
struct intel_context *intel = &brw->intel;
GLuint nr = 2;
GLuint channel;
- int base_reg; /* For gen6 fb write with no header, starting from color payload directly!. */
/* Reserve a space for AA - may not be needed:
*/
@@ -1428,11 +1427,6 @@ void emit_fb_write(struct brw_wm_compile *c,
*/
brw_push_insn_state(p);
- if (intel->gen >= 6)
- base_reg = nr;
- else
- base_reg = 0;
-
for (channel = 0; channel < 4; channel++) {
if (intel->gen >= 6) {
/* gen6 SIMD16 single source DP write looks like:
@@ -1524,15 +1518,20 @@ void emit_fb_write(struct brw_wm_compile *c,
}
if (intel->gen >= 6) {
- /* Subtract off the message header, since we send headerless. */
- nr -= 2;
+ /* Load the message header. There's no implied move from src0
+ * to the base mrf on gen6.
+ */
+ brw_push_insn_state(p);
+ brw_set_mask_control(p, BRW_MASK_DISABLE);
+ brw_MOV(p, brw_message_reg(0), brw_vec8_grf(0, 0));
+ brw_pop_insn_state(p);
}
if (!c->runtime_check_aads_emit) {
if (c->aa_dest_stencil_reg)
emit_aa(c, arg1, 2);
- fire_fb_write(c, base_reg, nr, target, eot);
+ fire_fb_write(c, 0, nr, target, eot);
}
else {
struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));